pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Lars-Peter Clausen	f02ba999ae	axi_dmac: Add support for DMA bus widths other than 64 bit There were a few place in the core where it assumed a 64-bit wide bus. Make this configurable using parameters. The patch also adds support for having different DMA bus widths on the source and destination side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2014-03-13 13:20:10 +01:00
Lars-Peter Clausen	6da9c65a08	axi_dmac: Add support for zero latency transfer switching Right now there is always a period of one clock cycle where we can not transfer any data when switching between two transfers. This patch modifies the data mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2014-03-07 18:39:20 +01:00
Adrian Costina	831c19ea84	Added axi_dmac, axi_fifo and misc files in library	2014-03-06 18:16:02 +02:00

Author

SHA1

Message

Date

Lars-Peter Clausen

f02ba999ae

axi_dmac: Add support for DMA bus widths other than 64 bit

There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

2014-03-13 13:20:10 +01:00

Lars-Peter Clausen

6da9c65a08

axi_dmac: Add support for zero latency transfer switching

Right now there is always a period of one clock cycle where we can not transfer
any data when switching between two transfers. This patch modifies the data
mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

2014-03-07 18:39:20 +01:00

Adrian Costina

831c19ea84

Added axi_dmac, axi_fifo and misc files in library

2014-03-06 18:16:02 +02:00

3 Commits (7cdab9b5b0ba087c3cb495d8ae666895938be87e)