Rejeesh Kutty
|
96969079ce
|
a5soc: fixes for 14.0 and spi conflicts
|
2014-08-11 16:46:37 -04:00 |
Istvan Csomortani
|
902d5b0da2
|
prcfg: Update fmcomms2_pr for ZC706
|
2014-08-05 17:55:31 +03:00 |
Istvan Csomortani
|
9dfbf4a9a6
|
prcfg: Update the prcfg logic to the new ad9361 interface
|
2014-08-05 17:54:37 +03:00 |
Adrian Costina
|
e9f8c0fb5f
|
fmcomms5: ZC706 modified constraints for linux build machines
|
2014-08-01 18:09:55 +03:00 |
Adrian Costina
|
6c6cab0e16
|
fmcomms2: ZC706 modified constraints for linux build machines
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
|
2014-08-01 17:34:36 +03:00 |
Rejeesh Kutty
|
663588eeaf
|
daq2/kcu105: working ddr version
|
2014-07-29 09:15:30 -04:00 |
Adrian Costina
|
9cdd4107cd
|
fmcomms5: ZC702: add reset_b and fixed system_top
|
2014-07-25 15:24:11 +03:00 |
Rejeesh Kutty
|
7bee85423d
|
c5soc: removed stp/cdf files
|
2014-07-24 20:53:08 -04:00 |
Rejeesh Kutty
|
59759a8ab3
|
c5soc: working hdl version
|
2014-07-24 20:51:41 -04:00 |
Adrian Costina
|
7000897031
|
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
|
2014-07-24 19:57:22 +03:00 |
Adrian Costina
|
a68f634de9
|
fmcomms5: Added resetb for the second AD9361
|
2014-07-24 17:31:30 +03:00 |
Istvan Csomortani
|
49a77c0413
|
prcfg: Generate configuration files to *.bin
|
2014-07-24 09:43:00 +03:00 |
Rejeesh Kutty
|
db2386a351
|
daq2/kcu105: latest mig updates
|
2014-07-23 16:25:55 -04:00 |
Istvan Csomortani
|
db1c931736
|
ad9625_plddr: PL DDR3 fixes
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
|
2014-07-23 19:34:44 +03:00 |
Istvan Csomortani
|
4da8100fe5
|
ad9625_plddr: Delete trailing whitespaces.
|
2014-07-23 19:31:07 +03:00 |
Rejeesh Kutty
|
c0e31aa6c2
|
daq2: latest hardware
|
2014-07-21 09:06:57 -04:00 |
Rejeesh Kutty
|
e3320c43cb
|
fmcomms2/c5soc: programmer file
|
2014-07-21 09:06:55 -04:00 |
Rejeesh Kutty
|
9b9e0c6a56
|
fmcomms2/c5soc: signal tap
|
2014-07-21 09:06:54 -04:00 |
Rejeesh Kutty
|
65879d621f
|
daq2: updates for the new hardware
|
2014-07-21 09:06:53 -04:00 |
Istvan Csomortani
|
2b6ce1e504
|
zc706_plddr3 : Fix axi_fifo2s_axi_mrst net
|
2014-07-21 15:10:36 +03:00 |
Rejeesh Kutty
|
2955b9db78
|
fifo2s: flush if no request, c5soc: 14.0
|
2014-07-15 16:25:33 -04:00 |
Rejeesh Kutty
|
e7d5d79e42
|
daq2/kcu105: gth up and running - as it is commit
|
2014-07-10 10:56:37 -04:00 |
Istvan Csomortani
|
085512a738
|
fmcomms2_pr: Fix the source path for prcfg_setup
|
2014-07-10 17:54:41 +03:00 |
Istvan Csomortani
|
95701fbd0e
|
fmcomms2_pr : PR initial check in
|
2014-07-10 10:41:48 +03:00 |
Rejeesh Kutty
|
b434fe6dd5
|
fmcomms5: register map changes
|
2014-07-08 16:57:43 -04:00 |
Adrian Costina
|
39ac29bb01
|
AD9361: Altera, modified address width so that all registers are accessible
Modified qsys project with the new address span
|
2014-07-08 10:41:51 +03:00 |
dbogdan
|
10c21a343a
|
fmcomms2/c5soc: Fixed the spim0_ss_in_n value.
|
2014-07-08 10:07:31 +03:00 |
dbogdan
|
c53b257ab1
|
fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments.
|
2014-07-07 22:28:25 +03:00 |
Rejeesh Kutty
|
c75e6b3043
|
kcu105 pwr-good removed
|
2014-07-07 09:56:13 -04:00 |
Rejeesh Kutty
|
f2bf5ced04
|
ad9625: register map updates
|
2014-07-03 14:30:03 -04:00 |
Rejeesh Kutty
|
f94cbbb0aa
|
daq2: register map updates
|
2014-07-03 12:36:37 -04:00 |
Rejeesh Kutty
|
a388ccab0a
|
fmcomms2/c5soc: initial checkin
|
2014-07-02 14:56:00 -04:00 |
Rejeesh Kutty
|
9a08189b93
|
c5soc: initial a5soc copy
|
2014-07-01 13:09:38 -04:00 |
Rejeesh Kutty
|
c1b7fc17f5
|
c5soc: initial a5soc copy
|
2014-07-01 13:05:26 -04:00 |
Rejeesh Kutty
|
60dd14bcdb
|
a5soc: removed jtag master control
|
2014-07-01 12:27:37 -04:00 |
Rejeesh Kutty
|
ba7955c531
|
fmcomms2: register map modifications
|
2014-06-26 10:09:03 -04:00 |
Rejeesh Kutty
|
92e525d573
|
ad9250: register map updates
|
2014-06-25 15:24:48 -04:00 |
Rejeesh Kutty
|
e38813fa9f
|
fifo- monitor status signals
|
2014-06-25 12:15:13 -04:00 |
Rejeesh Kutty
|
57bb3705f2
|
zc706-plddr3: read changes to lower dma clock
|
2014-06-25 09:20:58 -04:00 |
Istvan Csomortani
|
3d8d576532
|
prcfg_script: Update the PR flow script
+ Make part global
+ No need the Explore directive on implementation
+ Fix some reference to pr module
+ Fix the pr_verify function
|
2014-06-13 20:33:59 +03:00 |
Rejeesh Kutty
|
7efd6149f8
|
daq2: initial checkin
|
2014-06-12 15:54:25 -04:00 |
Rejeesh Kutty
|
b1b9067512
|
ad9625x2_fmc: added multi-sync support
|
2014-06-12 15:45:35 -04:00 |
Rejeesh Kutty
|
6ea7dd7fc3
|
kcu105: pwr-good added
|
2014-06-12 15:22:31 -04:00 |
Adrian Costina
|
6e444559b5
|
usdrx1: global clock fix
|
2014-06-10 18:09:49 +03:00 |
Rejeesh Kutty
|
2d27f88588
|
ad9625_fmc, ad9625x2_fmc: initial checkin
|
2014-06-09 16:40:48 -04:00 |
Adrian Costina
|
bef6a9c32c
|
axi_ad9361: Split dma data into individual channels for both ADC and DAC
|
2014-06-07 17:15:31 +03:00 |
Adrian Costina
|
2837d788a6
|
mitx045: Added I2S core to the base design
|
2014-06-06 17:53:47 +03:00 |
Istvan Csomortani
|
bd8d355b05
|
scripts: Update adi_prcfg_project.tcl
Define a new parameter for the prcfg_init_workspace process:
prcfg_name_list.
|
2014-06-06 15:00:23 +03:00 |
Rejeesh Kutty
|
cf56a568c6
|
kcu105: GTH updates
|
2014-06-05 14:27:38 -04:00 |
Istvan Csomortani
|
f452e40192
|
scripts: Initial check in of non-project flow
These processes are used for projects with partial
reconfiguration. The used design flow in these cases is the
non-project (batch) design flow.
|
2014-06-05 14:33:27 +03:00 |
Adrian Costina
|
45325b7c0d
|
mitx045: minor changes in common and ADV7511 projects
|
2014-06-03 19:24:12 +03:00 |
Rejeesh Kutty
|
f695a45394
|
global clock fix
|
2014-06-03 09:23:23 -04:00 |
Adrian Costina
|
f217139770
|
fmcomms2: added project for mini_itx, xc7z045 version
|
2014-06-02 14:06:10 +03:00 |
Adrian Costina
|
c52327d0c6
|
common,adv7511: Added mitx045 platform.
|
2014-06-02 11:08:03 +03:00 |
Rejeesh Kutty
|
877b81a373
|
ad9625/vc707: working version
|
2014-05-30 15:07:23 -04:00 |
Rejeesh Kutty
|
c789dce77e
|
ad9625/zc706: added pl ddr3 fifo changes
|
2014-05-29 12:59:29 -04:00 |
Rejeesh Kutty
|
56ddce1e8c
|
dmac: create fifo interface to avoid being treated as axi control stream
|
2014-05-27 10:25:14 -04:00 |
Istvan Csomortani
|
1d53d79e25
|
fmcomms2/common: Fix ad9361's interface
Loopback the l_clk to clk. l_clk is the device sampling clock, clk is used to
synchronize the cores in case of a multiple device configuration.
|
2014-05-21 10:09:54 +03:00 |
Istvan Csomortani
|
25e4520726
|
fmcomms2/common: Delet trailing white spaces
|
2014-05-21 09:47:37 +03:00 |
Rejeesh Kutty
|
bab90a19c2
|
fmcomms5/zc702: removed unused ila cores
|
2014-05-20 14:42:48 -04:00 |
Rejeesh Kutty
|
7e6b4ea9d0
|
fmcomms5: ignore only common clock to external clocks
|
2014-05-19 20:38:41 -04:00 |
Rejeesh Kutty
|
9a36075324
|
moved fmcomms5
|
2014-05-19 13:49:49 -04:00 |
Rejeesh Kutty
|
f73819f4d4
|
zc706: pl ddr3 initial checkin
|
2014-05-13 16:19:53 -04:00 |
Rejeesh Kutty
|
f3f8374c75
|
ad9671: 2lane version
|
2014-05-08 18:33:26 -04:00 |
Istvan Csomortani
|
c5b3dd3643
|
vc707 base : tcl update
- Added missing address space
- Connect the sys_audio_clkgen/reset
|
2014-05-08 12:30:25 +03:00 |
Rejeesh Kutty
|
3ac1da178e
|
kcu105: sane except for ddr4/ethernet
|
2014-05-06 15:39:05 -04:00 |
Rejeesh Kutty
|
51c0ee1e20
|
ml605: tcl updates
|
2014-05-06 09:29:21 -04:00 |
Rejeesh Kutty
|
e7cbaca216
|
ml605: initial checkin
|
2014-05-05 11:24:12 -04:00 |
Rejeesh Kutty
|
53af7f3c1f
|
ml605: initial checkin
|
2014-05-05 11:20:26 -04:00 |
Rejeesh Kutty
|
4d4f66fbdd
|
a5soc: increase pipeline for qsys
|
2014-05-04 10:38:53 -04:00 |
Rejeesh Kutty
|
b55d0d7ad1
|
a5soc: constraints for false paths
|
2014-04-30 16:14:30 -04:00 |
Rejeesh Kutty
|
a10043c4f4
|
kcu105: base complete with ethernet errors
|
2014-04-30 14:41:43 -04:00 |
Rejeesh Kutty
|
ef60cce15e
|
kcu105: added
|
2014-04-30 14:41:40 -04:00 |
Rejeesh Kutty
|
be69c0c330
|
kcu105: initial checkin
|
2014-04-30 14:41:39 -04:00 |
Rejeesh Kutty
|
9900a56fa5
|
kcu105: initial checkin
|
2014-04-30 14:41:37 -04:00 |
Rejeesh Kutty
|
0b1ce14842
|
a5soc: basic hardware build
|
2014-04-30 12:40:27 -04:00 |
Rejeesh Kutty
|
99d66e7580
|
a5soc: initial-copy version
|
2014-04-30 12:40:26 -04:00 |
Rejeesh Kutty
|
681e4239df
|
ad9671/a5gt: subclass-0 version
|
2014-04-28 21:31:21 -04:00 |
Rejeesh Kutty
|
06873aeddb
|
ad9671/a5gt: subclass-0 version
|
2014-04-28 21:31:20 -04:00 |
Rejeesh Kutty
|
d66f256f1c
|
9671/a5gt: 9671-sc1 version
|
2014-04-28 21:31:19 -04:00 |
Rejeesh Kutty
|
f55288ef5d
|
ad9671: altera - base changes
|
2014-04-28 21:31:18 -04:00 |
Rejeesh Kutty
|
2e7bf190b5
|
initial checkin-9250 copy
|
2014-04-28 21:31:15 -04:00 |
Adrian Costina
|
01de117b5f
|
motor_control: Changed controller to PID controller. Some estetic changes
|
2014-04-28 17:57:51 +03:00 |
Rejeesh Kutty
|
dfc2bba335
|
ad9671: updates to allow default adc setup routines
|
2014-04-23 16:39:28 -04:00 |
Rejeesh Kutty
|
a1bcf345c6
|
ad9671: fix spi connections
|
2014-04-21 13:46:44 -04:00 |
Adrian Costina
|
213e852e11
|
motor_control: Initial commit
|
2014-04-18 18:57:18 +03:00 |
Adrian Costina
|
ba44ee63be
|
fmcomms1: modified the fmcomms1_bd.tcl to make it compatible with latest wfifo
|
2014-04-14 17:04:04 +03:00 |
Istvan Csomortani
|
179d6d601c
|
adi_board.tcl : Use 'global' instead of '$::'
|
2014-04-14 11:45:35 +03:00 |
Rejeesh Kutty
|
38126c404c
|
usdrx1: spi signal definitions
|
2014-04-11 14:28:23 -04:00 |
Rejeesh Kutty
|
06b28d2e24
|
ad9671: compile fixes
|
2014-04-11 14:28:22 -04:00 |
Rejeesh Kutty
|
e92e6b2fd5
|
ad9671_fmc: changed for ad9671-fmc
|
2014-04-11 14:28:21 -04:00 |
Rejeesh Kutty
|
72e318a247
|
ad9671_fmc: initial checkin
|
2014-04-11 14:28:20 -04:00 |
ATofan
|
99ef34936f
|
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
|
2014-04-11 18:14:08 +03:00 |
Adrian Costina
|
d0f04fd788
|
fmcomms1: Commit AC701 and VC707 projects
|
2014-04-11 17:35:25 +03:00 |
Istvan Csomortani
|
c718169f27
|
adi_board.tcl : Fix the address assignment command
A lot of cores have more than one address segments, therefor need
to filter out the segment of the axi lite interface
|
2014-04-11 16:14:56 +03:00 |
Istvan Csomortani
|
cf5b9b51fd
|
adi_board.tcl : Fix spi ports and hp clocks
|
2014-04-11 15:31:12 +03:00 |
Istvan Csomortani
|
37e2059fd0
|
adi_board.tcl : General update
- Split the adi_dma_interconnect to two procedure:
adi_dma_interconnect and adi_hp_assign
- Fix the adi_spi_core
- Fix the adi_interconnect_lite
|
2014-04-10 18:29:14 +03:00 |
Rejeesh Kutty
|
96541f0a7f
|
usdrx1: zc706 updated for usdrx1
|
2014-04-10 11:05:13 -04:00 |
Rejeesh Kutty
|
6f36f74eea
|
usdrx1: common board files
|
2014-04-10 11:05:11 -04:00 |
Rejeesh Kutty
|
ac1c145a61
|
usdrx1: initial checkin
|
2014-04-10 11:05:10 -04:00 |