2 Commits (7ae2bc628529b3592294bc1bb35bb9d6c527a5e1)

Author	SHA1	Message	Date
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Rejeesh Kutty	2b7c976be5	xcvr- altera/xilinx split	2016-08-04 13:26:10 -04:00