6d504d14cf
fmcomms8: zcu102: Fix lane swapping
2021-02-05 15:07:09 +02:00
769b195800
util_axis_fifo: Add support for tlast
2021-02-05 13:35:06 +02:00
0fd5590e56
ad9081_fmca_ebz: a10soc: Initial version
...
Parametrizable project with default profile of:
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2021-02-05 10:24:59 +02:00
6e6c51dd27
common/a10soc: Bridge support
2021-02-05 10:24:59 +02:00
f0b753321a
common/intel: Add util_adcfifo integration script
2021-02-05 10:24:59 +02:00
3041e77659
ad40xx/zed: Update constraints
2021-02-04 11:04:32 +02:00
05469a011c
ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA
2021-02-04 11:04:32 +02:00
93f46ef6e3
spi_engine_execution: Add constraints file
2021-02-04 11:04:32 +02:00
ab10bd136e
spi_engine_execution: Add echoed SCLK support
...
There are boards (e.g. AD4630-24) which take the SCLK and echo back to
the FPGA through a level shifter - doing this removes the effect of
round-trip timing delays from the level shifter. This is commonly done
whenever isolators are used since they are very slow.
By setting the ECHO_SCLK parameter to 1, the IP will use the incoming
echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still
synchronous to the SPI clock, and it's generated after the last valid
SDI latch.
The designer's responsibility is to time the SDI shift registers in order to
respect the design requirements.
2021-02-04 11:04:32 +02:00
6f4053f3b0
util_adxcvr: Fix PRBS synchroniser typo
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The control lines for TX PRBS must be synchronized using the TX clock.
2021-01-29 14:01:25 +02:00
dd4c8d6807
adrv9001/zcu102: Add debug header
2021-01-26 15:22:41 +02:00
728904af09
adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing
2021-01-26 15:22:41 +02:00
bae7e48c50
adrv9001/common: Run DMAs @ 100MHz
2021-01-26 15:22:41 +02:00
714d557245
axi_adrv9001: Add opt-in synthesis parameters
2021-01-26 15:22:41 +02:00
31929167d3
axi_adrv9001: Use global clocks for divided down clock
2021-01-26 15:22:41 +02:00
8476993c1b
ad_pnmon: Fix zero checking when valid not constant
2021-01-26 15:22:41 +02:00
c7046a6d72
axi_adrv9001:axi_adrv9001_rx_channel: fix ramp signal checking
2021-01-26 15:22:41 +02:00
f68c222489
cn0501/coraz7s: Fix sysid
2021-01-22 15:40:37 +02:00
669217db8b
ad_tdd_control: Avoid single pulses if tx_only or rx_only
2021-01-20 13:00:01 +02:00
843c2565f7
up_tdd_cntrl: Split large synchronizer in smaller ones
...
This will help placement.
2021-01-20 13:00:01 +02:00
54c2cf7d12
ad_tdd_control: Fix rx/tx only behavior
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When tx_only disable rx_enable and vice-versa
2021-01-20 13:00:01 +02:00
bb44e5399f
adrv9001/zed: Connect TDD sync to PMOD JA1
2021-01-20 13:00:01 +02:00
a47cc59c67
common/up_tdd_cntrl: Fix read data when read is idle
2021-01-20 13:00:01 +02:00
3918d43cd1
adrv9001/zcu102: Add TDD sync to PMOD0 J55.1
2021-01-20 13:00:01 +02:00
fe9f72db9c
adrv9001/common: Export TDD mode signal
2021-01-20 13:00:01 +02:00
58f2eec127
axi_adrv9001: Export TDD mode
2021-01-20 13:00:01 +02:00
18b2a8b0a7
adrv9001/zed: Add TDD support
2021-01-20 13:00:01 +02:00
0c2745361b
adrv9001/zcu102: Add TDD support
2021-01-20 13:00:01 +02:00
afa3f11206
axi_adrv9001: Add TDD support
2021-01-20 13:00:01 +02:00
7e63113734
library/common/up_tdd_cntrl: Make address generic
2021-01-20 13:00:01 +02:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
da61515d41
ad40xx: Fix bd.tcl script
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
da9828a63e
ad9081:zcu102: Expose parameters to environment
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Allow setting project parameters from the environment.
2021-01-19 17:10:08 +02:00
d82f61b9af
util_axis_fifo: Add KEEP synthesis attribute for zerodeep CDC
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Vivado synthesis is optimizing out the zerodeep block, resulting untreated
clock domain crossing. Set KEEP attribute for the registers.
2021-01-19 14:28:07 +02:00
235fb4859a
usrpe31x: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
f1421c91ee
sidekiqz2: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
f68393ecb9
adrv936x: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
3e237459e3
pluto: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
d9639db991
m2k: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
e41ba7f6f5
adrv9009zu11eg: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
9ec3408c79
adi_project_xilinx: Fix the adi_project process
...
In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.
NOTE: In these case we should use adi_project_create directly in system_project.tcl.
2021-01-15 15:26:43 +02:00
b9ac8df503
project-xilinx.mk: Add *.hbs to clean list
2021-01-15 13:50:53 +02:00
067b57d404
vc707: Fix mdio intf
2021-01-15 13:50:53 +02:00
c54552d823
adi_project_xilinx: Add env var
...
add ADI_DISABLE_MESSAGE_SUPPRESION which disables
adi_xilinx_msg.tcl
projects/scripts/adi_project_xilinx.tcl
2021-01-15 13:50:53 +02:00
e252d538c2
adi_ip_xilinx: Add env var
...
add ADI_DISABLE_MESSAGE_SUPPRESION which
disables adi_xilinx_msg.tcl
2021-01-15 13:50:53 +02:00
ead4513ad6
adi_xilinx_msg: Downgrade Synth 8-2490
2021-01-15 13:50:53 +02:00
51b5e4f58b
tcl: Change Vivado version to 2020.1
...
handoff is now exported as .xsa
2021-01-15 13:50:53 +02:00
fbb2a0e1a0
de10nano: Add hps_conv_usb_n signal to stabilize UART lines
...
Without defining this signal, the UART lines receive garbage data
when no cable is connected to the J4 USB UART port.
The GPIO9 is enabled in the reference base design along with the
4MA CURRENT_STRENGTH constraint on the UART pins
2021-01-13 15:36:45 +02:00
dee108ba22
fmcomms8/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
Adrian Costina
Istvan Csomortani
Laszlo Nagy
Sergiu Arpadi