Commit Graph

2731 Commits (78999e154e166bee19ff5e3e7ad0d9e3d2360170)

Author SHA1 Message Date
stefan.raus d2ef1bcef5 library/commmon: Fix data width warnings
ad_tdd_control.v: Set ON and OFF local parameters on just one bit.
up_dac_common.v: Set CLK_EDGE_SEL parameter on just one bit.
2020-09-23 09:16:48 +03:00
Istvan Csomortani cba3c0f4f1 spi_engine_offload: Define status_sync interface 2020-09-15 18:14:23 +03:00
Istvan Csomortani 780579f3e9 spi_engine_offload: Delete trailing whitespaces 2020-09-15 18:14:23 +03:00
Istvan Csomortani b827322917 spi_engine_execution: Add missing parameter definition into hw.tcl script 2020-09-15 18:14:23 +03:00
Istvan Csomortani f67209e125 axi_spi_engine: Fix the hw.tcl script
Define both AXI4 Memory Mapped and microprocessor interface for the
reigster map, then activate/deactive one of it in fucntion of the memory
interface type parameter.

Define the missing status_sync interface, which should be connected to
the offload.
2020-09-15 18:14:23 +03:00
Istvan Csomortani f934ff7e4e axi_spi_engine: Add missing ports to every sub-module instance 2020-09-15 18:14:23 +03:00
Istvan Csomortani a5326cb3d2 axi_spi_engine: Refactoring sdi_fifo read outs
Context switching with a parameter is not a good idea. The simulator
may evaluate both branch of the IF statement, even though the inactive
branch may not be valid.

Use if..generate to make the code more robust for both synthesizers and
simulators.
2020-09-15 18:14:23 +03:00
AndreiGrozav 422d7c949c axi_hdmi_tx_vdma: Use only synchronous reset 2020-09-15 18:14:23 +03:00
AndreiGrozav 520a7ea972 axi_hdmi_tx: Update IP to latest HDL flow
Conflicts:
	library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
2020-09-15 18:14:23 +03:00
AndreiGrozav 585ed44983 Add 'SE Base' family to the supported FPGAs 2020-09-15 18:14:23 +03:00
Istvan Csomortani 85aeb915b4 spi_engine_offload: Start offload when DMA is ready 2020-09-15 12:03:48 +03:00
Istvan Csomortani 121ac2e97a spi_engine_interconnect: always construct must not contains mixed assignment types 2020-09-15 12:01:58 +03:00
Arpadi 4a28a4e856 sysid_intel: Added hw.tcl for sysid IP cores 2020-09-11 15:46:06 +03:00
AndreiGrozav 1e537b1083 axi_ad9963: Fix warnings
-fix missing connection warnings
-fix wrong bus width warning
2020-09-11 10:24:22 +03:00
AndreiGrozav 3d407a3ba5 axi_ad9467: Fix missing connection warnings 2020-09-11 10:24:22 +03:00
AndreiGrozav 5f0abc5099 axi_ad9361: Fix missing connection warnings 2020-09-11 10:24:22 +03:00
AndreiGrozav f2422080de axi_hdmi_tx: Fix warning on imageon
Remove an extra assignment to hdmi_vs register.
2020-09-11 10:23:53 +03:00
AndreiGrozav 498e07e640 ad_csc: Fix warning for axi_hdmi_tx
Converting from RGB to YCbCr takes one less stage than converting
from YCbCr to RGB color space.
Moving extra delay stage(5), of the sync signals to a particular
YCbCr to RGB color space conversion case.
2020-09-11 10:23:53 +03:00
AndreiGrozav f0a29a682f common/ad_ss_422to444.v: Fix warning
Using a localparam in a port declaration, causes the following warning:
"identifier 'DW' is used before its declaration".
2020-09-11 10:23:53 +03:00
AndreiGrozav 8d80b0f85f axi_logic_analyzer: Fix data width warning 2020-09-11 10:23:26 +03:00
Istvan Csomortani 1e5e859222 intel/axi_adxcvr: Use ad_ip_files process for source definition 2020-09-09 14:15:37 +03:00
Istvan Csomortani 256593623c intel/adi_jesd204: Add an additional pipeline stage to RX soft PCS 2020-09-09 14:15:37 +03:00
Istvan Csomortani 0e98527bad intel/adi_jesd204: Expose REGISTER_INPUTS parameter
Define INPUT_PIPELINE parameter, which can be used to activate the
REGISTER_INPUTS parameter of the PHY. This parameter will add an
additional register stage into the incoming parallel data stream.
It can be used to relax the timing margin between the PHY and Link modules.
2020-09-09 14:15:37 +03:00
Istvan Csomortani 72a4d54b76 jesd204_rx: Fix SDC constraint 2020-09-09 14:15:37 +03:00
Istvan Csomortani edbd9f7b8f jesd204_framework: Add Stratix10 support
This patch contains an initial effort to support the Stratix 10
architecture in our JESD204 framework.

Several instances were updated, doing simple context switching using the
DEVICE_FAMILY system parameter:

  - xcvr_reset_control
  - lane PLL (ATX PLL)
  - link PLL (fPLL)
  - native XCVR instance

Apart from the slightly different parameters of the instances above,
there were small differences at the reconfiguration Avalon_MM interface.

The link_pll_reset_control is required just for Arria10, so in case of
Stratix10 it isn't instantiated.

In Stratix 10 architecture there are several additional ports of the
xcvr_reset_control module that must be connected to the native XCVR
instance or tied to GND.

The following xcvr_reset_control ports were defined and connected to the
XCVR:

  - rx|tx_analogreset_stat
  - rx|tx_digitalreset_stat
  - pll_select
2020-09-09 14:15:37 +03:00
Stanca Pop 9c2cfb8c34 axi_generic_adc: Declare parameters before use 2020-08-31 15:58:35 +03:00
Laszlo Nagy 5599fda3b6 library/common/ad_dds: Fix indentation 2020-08-27 13:37:53 +03:00
Laszlo Nagy 5d803d6b6e library/common/ad_dds: Fix initialization when 'valid' not constant
If dac_valid is not a constant '1' it gets synchronized with the
dac_data_sync signal. This causes that dac_valid never asserts while
dac_data_sync is high, this way skipping the phase initialization.
2020-08-27 13:37:53 +03:00
Rodrigo Alencar 99fec4fab3 axi_i2s_adi: create friendly xgui files
Signed-off-by: Rodrigo Alencar <455.rodrigo.alencar@gmail.com>
2020-08-25 09:55:31 +03:00
Laszlo Nagy 64f6762a05 library:axi_adrv9001: Initial version
ADRV9001 interfacing IP supports the following modes on Xilinx devices:

A              B  C       D       E       F      G        H
CSSI__1-lane   1  32      80      80      2.5    SDR      8
CSSI__1-lane   1  32      160     80      5      DDR      4
CSSI__4-lane   4  8       80      80      10     SDR      2
CSSI__4-lane   4  8       160     80      20     DDR      1
LSSI__1-lane   1  32      983.04  491.52  30.72  DDR      4
LSSI__2-lane   2  16      983.04  491.52  61.44  DDR      2

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
LSSI - LVDS Source Synchronous Interface

Intel devices supports only CSSI modes.
2020-08-24 17:49:12 +03:00
Laszlo Nagy 8e243b6d32 up_adc_common: Expose up version of r1_mode 2020-08-24 17:49:12 +03:00
Laszlo Nagy 7023639b8f library/common/up_dac_common: Sync dac_rst to control set
De-assert dac_rst together with an updated control set.
This allows writing the control registers before releasing the reset.
This is important at start-up when stable set of controls is required.
2020-08-24 17:49:12 +03:00
Laszlo Nagy f886c246cd library/common/up_dac_common: Add registers to control interface
DDR/SDR - selectable input rate
 number of lanes - number of active lanes that transport data
                  (2 LVDS diff lanes counts as one)
2020-08-24 17:49:12 +03:00
Laszlo Nagy 32be451b98 library/common/up_adc_common: Sync adc_rst to control set
De-assert adc_rst together with an updated control set.
This allows writing the control registers before releasing the reset.
This is important at start-up when stable set of controls is required.
2020-08-24 17:49:12 +03:00
Laszlo Nagy 75c037fcca library/common/up_adc_common: Add registers to control interface
DDR/SDR - selectable input rate
number of lanes - number of active lanes that transport data
                  (2 LVDS diff lanes counts as one)
2020-08-24 17:49:12 +03:00
Laszlo Nagy 05167e2c2b ad_pnmon: Allow patterns with zero as valid data
Allow monitoring of non-PN patterns which have zeros in it.
e.g. nible-ramp, full range ramp.

Singular zeros got ignored if not out of sync, while OOS_THRESHOLD
consecutive zeros or non-matching data asserts the out of sync line.
2020-08-24 17:49:12 +03:00
Laszlo Nagy bf06a5c08f ad_pngen: Generic PN generator
Parametrizable PN generator, can generate any polynomial with the help of a mask.
2020-08-24 17:49:12 +03:00
Istvan Csomortani 3bd8b73028 axi_spi_engine: Fix value range for ID parameter 2020-08-24 16:45:02 +03:00
Istvan Csomortani 46419f8d09 spi_engine: Fix ip scripts for regmap, offload and execution
Fix the *_ip.tcl scripts for axi_spi_engine and spi_engine_offload
module.

In case of a bool parameters the value_format and value properties must
be set for both user and hdl paramters. If not, in the generated verilog
code the tool will use "true" or "false" strings, instead of 0 or 1.
2020-08-24 16:45:02 +03:00
Istvan Csomortani 1c7043c707 axi_spi_engine: Update IPXACT GUI layout 2020-08-19 10:46:46 +03:00
Istvan Csomortani c8fb3a1846 spi_engine_execution: Update IPXACT GUI layout 2020-08-18 08:53:32 +03:00
Istvan Csomortani d1a6f87adb spi_engine_interconnect: Update IPXACT GUI layout 2020-08-18 08:53:14 +03:00
Istvan Csomortani eaf3e97450 spi_engine_offload: Update IPXACT GUI layout 2020-08-18 08:52:58 +03:00
Stanca Pop 5d4d34477c spi_engine: Add Intel Support 2020-08-17 16:37:21 +03:00
Istvan Csomortani 11947f2e7e spi_engine_execution: code refactoring
The added modification do not chnage the functionality of the module.
2020-08-13 10:01:16 +03:00
Istvan Csomortani 45d806ff11 spi_engine_execution: Fix sdi_shift_reg reset and command latching 2020-08-13 10:01:16 +03:00
AndreiGrozav 26224186c1 ad_dds: Fix typo
Fix for Intel projects
2020-08-13 09:40:46 +03:00
AndreiGrozav 47fa86cfd6 axi_logic_analyzer: Optimize the input data path
The input data path has a delay section that compensates for the ADC path delay.
By using a Dynamic Shift Registers coding style we can improve/change the
resource utilization on m2k:
          Before     After    Resources
LUT       10097      10048     48 (0.28%)
LUTRAM    516        540      -24 (-0.4%)
FF        15285      14803    482 (1.37%)
2020-08-13 07:01:19 +03:00
AndreiGrozav 58e0044643 axi_adc_trigger: Use valid in data delay stage
This is required to match the delays in the data path to internal/external
trigger path.
2020-08-13 07:01:19 +03:00
AndreiGrozav c797a2e14f axi_adc_decimate: Export signals indicating the rate
- oversampling_en signal
- filter mask value

Those signals will be used by the axi_adc_trigger.
2020-08-13 07:01:19 +03:00
AndreiGrozav 2e0ba5bffd axi_logic_analyzer: Auto sync to ADC path
The number of delay taps in the LA data path can be controlled manually, from
the regmap or automatically, according to the axi_adc_decimate's rate.

Moreover, because the rate is configure by software, and the time of
initialization, is different for the ADC path and LA path. There is an
uncertainty of plus/minus one sample between the two. Because ADC and LA
paths share the same clock we can easily synchronize the two paths. We
can't use reset, because the rate generation mechanism is different
between the two. So the ADC path is used as master valid generator and we
can use it to drive the LA path.
The synchronization is done by setting the rate source bit. This
mechanism can only be used if the desired rate for both path is equal,
including oversampling fom ADC decimation.
2020-08-13 07:01:19 +03:00
Laszlo Nagy d2b1164567 axi_dmac: Add interface description register
Adds information on:
  - Log 2 of interface data widths in bits
  - Interface type (0 - Axi MemoryMap, 1 -  AXI Stream, 2 - FIFO ) .
Lets the driver discover interface widths and interface type settings,
this will deprecate the corresponding device tree properties.

This is useful in case of parametrized projects where the width of
the datapath is changing. This change will allow the use of a generic
device tree node.

Updated version to 4.3.a
2020-08-12 17:50:16 +03:00
Laszlo Nagy 04fed45e54 util_cpack2: support for 64 channels 2020-08-11 10:37:59 +03:00
Laszlo Nagy b49928fca6 ad_ip_jesd204_tpl_adc: add support for 64 channels 2020-08-11 10:37:59 +03:00
Laszlo Nagy 2ca09adaf7 ad_ip_jesd204_tpl_dac: expand address space to accomodate 64 channels 2020-08-11 10:37:59 +03:00
Laszlo Nagy 59c2e581a2 util_upack2: support for 64 channels 2020-08-11 10:37:59 +03:00
Laszlo Nagy e698b286e5 jesd204: DAC TPL to support 64 channels 2020-08-11 10:37:59 +03:00
Istvan Csomortani fe90fc7e57 axi_ad9361: add_instance command must have a version attribute 2020-08-11 10:14:18 +03:00
Istvan Csomortani 0c7d85ac87 axi_laser_driver: Fix IP paramtere editor error
The parameter property 'type' cannot be modified after
adding the parameter.
2020-08-11 10:14:18 +03:00
Istvan Csomortani f38b9d44b9 util_adcfifo: Update the interfaces for the asymetric memory 2020-08-11 10:14:18 +03:00
Istvan Csomortani f624d5df40 intel_mem_asym: Update the interface definitions
The ram_2port IP has different interface names in Quartus PRO and
Quartus Standard.

Update the interface names for the support Quartus PRO.
2020-08-11 10:14:18 +03:00
Istvan Csomortani 2198320981 intel_mem_asym: add_instance command must have a version attribute 2020-08-11 10:14:18 +03:00
Istvan Csomortani 0de5039b96 avl_dacfifo: add_intance command must have a version attribute 2020-08-11 10:14:18 +03:00
Istvan Csomortani 3e6d9ee019 adi_jesd204: Delete redundant connections 2020-08-11 10:14:18 +03:00
Istvan Csomortani e856a99e49 adi_jesd204: add_instance command must have a version attribute 2020-08-11 10:14:18 +03:00
Istvan Csomortani 53e07c5d29 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
AndreiGrozav 9122d98132 adi_intel_device_info_enc.tcl: Fix typo 2020-08-10 18:30:46 +03:00
Laszlo Nagy 4e438261aa ad_serdes_out: Add CMOS support 2020-08-07 08:31:19 +03:00
Laszlo Nagy 837475db0d ad_serdes_in: Add CMOS support 2020-08-07 08:31:19 +03:00
Laszlo Nagy e6b9e21ad1 ad_serdes_out: Add tristate option 2020-08-07 08:31:19 +03:00
Laszlo Nagy c5c772127d up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable
US/US+ devices have IDELAY/ODELAY with 512 taps. This requires wider
control value for delay selection. 9 bits contrary to 5 on 7series.
2020-08-07 08:31:19 +03:00
Laszlo Nagy 37d378c753 common/ad_serdes_out.v: Add US/US+ support 2020-08-07 08:31:19 +03:00
Laszlo Nagy 65d39b9164 common/ad_serdes_in.v: Add US/US+ support 2020-08-07 08:31:19 +03:00
AndreiGrozav 4972e5c42d axi_dac_interpolate: oversampling optimization
Optimize the oversampling mechanism.
The behavior of the axi_dac_interpolate was changing if a debug module was
added to the core.
The current code has a better utilization and reliability.
2020-08-05 13:01:05 +03:00
AndreiGrozav d39ed3d4db axi_dac_interpolate: Fix oversampling by 2
When using an oversampling of 2 for axi_dac_interpolate the rate was
the same as with oversampling by 1(bypassing).

This commit removes the bypass for the ratio of 2.
2020-08-05 13:01:05 +03:00
AndreiGrozav a7a131cb36 ad_dds: Fix noise caused by dac_data_sync
For projects where the clock ratio between the sampling clock and core clock
is higher than 2, the ad_dds generates a number of samples equal with
the clock ratio. There is a phase offset between the samples, proportional
with the requested DDS frequency.
In scenarios where the DDS out frequency is closer to the upper
limit(Nyquist) and/or the clock ratio is also greater than 2 and the
dac_data_sync reminds low for an extended period of time, the DAC will
receive at each core clock period, a number of samples equal with the
clock ratio and with an amplitude influenced by the DDS out frequency.
In most cases similar with a sawtooth signal.

With this commit we ensures that samples received by the DAC are 0 for
the period where dac_data_sync signal is high. Only when the signal
transitions to low, the phase accumulator is initialized and the phase
information is passed to the phase to amplitude converter.

Another issue can appear when the sync signal is too short; less then
CLK_RATIO * clock cycles. Because the phase accumulator will not
synchronize at all stages, the final result will be a random combination of
sine-waves. Added a minimum sync pulse after the dac_data_sync is set
low.
2020-08-04 13:08:07 +03:00
Laszlo Nagy 6ca6257341 jesd204_rx: Increment version to 1.04.a
- support for frame alignment check
- support for interrupt on frame alignment error
- support for interrupt on unexpected lane status error
2020-07-31 11:43:41 +03:00
Laszlo Nagy 87b67ced17 jesd204_rx: Interrupt for unexpected lane status error 2020-07-31 11:43:41 +03:00
Laszlo Nagy 5e16eb85bb jesd204_rx: Generate interrupt on frame alignment error
When frame alignment error monitoring is enabled and error threshold is met
at least for one lane, generate an interrupt so software can reset the link and
do further bring-up steps.
2020-07-31 11:43:41 +03:00
Laszlo Nagy cf145ca961 axi_adxcvr: Reset status if PLL lock is lost
In case something happens with the reference clock of the CPLL or QPLL,
they might lose the locking. The status should reflect that.
2020-07-31 11:43:41 +03:00
Laszlo Nagy 15e14c76b9 jesd204_rx: Don't auto reset on frame alignment error by default
Let software handle the error case by default. Other steps might be
required to bring-up properly the link if one shot SYSREF is used.
2020-07-31 11:43:41 +03:00
Matt Blanton 1e04b2e2f2 jesd204_rx: Add RX frame alignment character check
Add support for RX frame alignment character checking when scrambling is enabled and
for link reset on misalignment.
Add support for xcelium simulator to jesd204/tb
2020-07-31 11:43:41 +03:00
AndreiGrozav ef5f29e66b m2k: Pattern Generator add instrument triggering
The Pattern generator is part of the axi_logic_analyzer core.
The trigger signal can be internal (Oscilloscope or Logic Analyzer) or
external(TI or TO pins).
2020-07-23 18:22:38 +03:00
AndreiGrozav ad4439433d axi_logic_analyzer: Add trigger disable condition
The trigger disable condition will be used as default
or last available option in the trigger out source selection.
2020-06-26 10:47:15 +03:00
AndreiGrozav 3e91078af0 axi_adc_trigger: Add trigger disable condition
Add trigger disable condition.
Set the trigger blocking/disable condition as the default condition in
the trigger selection multiplexer.
2020-06-26 10:47:15 +03:00
Laszlo Nagy 2e5a4eb684 jesd204: update README to reflect rev C 2020-06-23 13:52:35 +03:00
Istvan Csomortani 51ebe6b35d spi_engine_execution: Latch sdx_enabled
The sdo_enabled and sdi_enabled control lines are generated from the
current state of the CMD bus.

In case of a delayed SDI latching the sdi_enabled can be deasserted at
the moment of the last valid bit, losing the generation of the sdi_data_valid
signal, which eventually cause a data loss, or even deadlock  on software driver.

To make the logic mode robust, latch the value of the CMD[9:8] at every
transfer command. Doing so the sdo_enabled and sdi_enabled control lines will
store the last active transfer command state and they will be
independent of the current state of the CMD bus. This way we can add
longer time delay to the SDI latching if it's necessary.
2020-06-18 15:46:06 +03:00
Istvan Csomortani e0d47645de spi_engine_execution: Optimize SDI latch delay logic 2020-06-18 15:46:06 +03:00
Istvan Csomortani d4c393332a ad_ip_jesd204_tpl: TPL has and address space of 4KB 2020-05-25 11:55:40 +03:00
Laszlo Nagy bff8a9fafb scripts/jesd204.tcl: rename tpl core instance
Having the same name for dac and adc TPLs creates conflict in the
address segment naming having random names associated to the segments.
This causes difficulties during scripting of the project in test bench
mode.
2020-05-20 19:08:25 +03:00
Istvan Csomortani e7600eb552 ad7616_sdz: Fix the project, after SDI ports were merged
Update the project to support the SDI port merge patch: 4d54c7e
2020-05-20 11:44:22 +03:00
Istvan Csomortani 0402ce85e4 axi_spi_engine: Add pulse_width to the CNV configuration interface
The conversion start configuration interface can be used to configure
a PWM generator (util_pulse_gen) to generate CNV for a precission ADC.
2020-05-19 14:18:21 +03:00
Istvan Csomortani 2506239a8a spi_engine: Add an additional register for SDI data 2020-05-19 09:28:34 +03:00
Istvan Csomortani 88d97eb8a5 spi_engine: Add NUM_OF_SDI value into register map
The value of the HDL parameter NUM_OF_SDI can be read out from the
register at address 0x0C. The same register contains the value of the
DATA_WIDTH.
The register has the following bit layout:
  [15: 0]  DATA_WIDTH
  [23:16]  NUM_OF_SDI
  [31:24]  8'b0
2020-05-19 09:28:34 +03:00
Istvan Csomortani 4d54c7e2d6 spi_engine_execution: Merge the SDI lines into one vector
This modification will help to support multiple SPI engine
execution setups (e.g. different NUM_OF_SDI) for the same project.
2020-05-19 09:28:02 +03:00
Istvan Csomortani 7b3d52436a spi_engine: Forward the offload's sync_id to the register map
Forward the offload's sync_id to the register map, by defining an
additional AXI stream interface between the offload and axi_spi_engine.
The last sync_id of the offload module can read out from the
register 0x00C4. It also can generate and interrupt if the irq mask is
configured accordingly.
2020-05-19 09:27:28 +03:00
Istvan Csomortani 3a029fc1f0 spi_engine_execution: Define all wires before use 2020-05-19 09:27:28 +03:00
Istvan Csomortani 5493274fb7 spi_engine_offload: Define constraints for CDC 2020-05-19 09:27:28 +03:00
Istvan Csomortani ff4ce95110 axi_spi_engine: Improve constraints 2020-05-19 09:27:28 +03:00
Istvan Csomortani 3c193296dd spi_engine_offload: Increment sync_id per transfer
Increment the sync_id value at each transfer. Initial value of the
sync_id is the value of the last SYNC command loaded into the command
buffer.
2020-05-19 09:27:28 +03:00
AndreiGrozav e63478dbad library/scripts/adi_ip_xilinx: Fix critical warning 2020-05-18 14:22:59 +03:00
Arpadi 907d6fcbd9 sysid_intel: Fixed axi_sysid module name 2020-05-18 14:19:42 +03:00
Istvan Csomortani 6535e5b2ba scripts/xilinx: Version mismatch is upgraded to ERROR
There is a major compatibility issue between 2019.1 and 2019.2.

The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.

If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
2020-05-15 12:16:35 +03:00
Adrian Costina 10c9f7a70d ad_ip_jesd204_tpl_dac: Add option for an external synchronization pin
The external synchronization signal should be synchronous with the
dac clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received

Added EXT_SYNC parameter to be able to keep the dac_sync original
behavior
2020-05-13 10:09:43 +03:00
Adrian Costina 5d4c6701d9 ad_ip_jesd204_tpl_adc: Add external synchronization
The external synchronization signal should be synchronous with the
adc clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received. While
the synchronization mechanism is armed, the adc_rst output signal is set

The current format should allow for the SYSREF signal to be used as
synchronous capture start, but will need to be disabled before the
synchronization mechanism is armed
2020-05-13 10:09:43 +03:00
sarpadi b92fb0a90d axi_fan_control: Fixed reset bug 2020-05-08 17:07:57 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Istvan Csomortani 8f2a223af9 spi_engine_execution: Fix the SDI latching
The commit 9ab88f1200 introduced a new
feature for the execution module, which provides the possibility to
delay the SDI line latch with one or more core clock cycle. Unfortunatly
the implementation was not correct and the SDI line was latched at the
wrong time.

This patch fix the aligment of the shift register and the SDI_DELAY parameter,
to latch the SDI line of the physical interface at the right time.

Improve the description of the feature.
2020-05-06 04:23:10 +01:00
Laszlo Nagy a32102b81c common/ad_iqcor: Fix for sample width smaller than 16
For converter resolution smaller than 16 when the core is disabled the
bypassed data was truncated. This patch should fix that.
2020-04-24 16:38:54 +03:00
Laszlo Nagy 70d139af7f jesd204/ad_ip_jesd204_tpl_dac: Fix Intel dependencies
Even if the IQ rotation is disabled in the projects all modules has to be
added to the list of dependencies to avoid compilation errors.
2020-04-08 10:50:28 +03:00
Laszlo Nagy 9450ddc66e library/common/ad_iqcor: fix for intel compilations 2020-04-06 20:28:11 +03:00
Laszlo Nagy ff2be680b3 library/common/ad_iqcor: fix whitespaces 2020-04-06 20:28:11 +03:00
Mathias Tausen 3857bdd16b axi_dmac: generalize version check
In some cases, the Vivado version can contain other characters than just
numbers. One such example is after applying the patch of AR# 71948,
which makes `version -short` return something like `2018.3_AR71948`.

This patch changes the version check to ignore anything after the first
two components of the version.
2020-04-03 11:18:59 +03:00
Laszlo Nagy af060700b8 jesd204/ad_ip_jesd204_tpl_dac: add I/Q roation 2020-04-03 11:16:37 +03:00
Laszlo Nagy 78aa56f9d2 common/ad_iqcor: fix alignment 2020-04-03 11:16:37 +03:00
Laszlo Nagy 007d03c034 common/ad_iqcor: process multiple samples per clock cycle 2020-04-03 11:16:37 +03:00
Maxim 341221dc91
jesd204: Update jesd204_tx_lane.v
Removed decoder for tx_ready.
2020-04-01 10:29:40 +03:00
AndreiGrozav 74221eb42c adi_xilinx_device_info_enc: Add new packages
Add definition for new ultrascale device packages.
The package information is used by software for xcvr calibration.
At the moment, the factors that are influencing the calibration for the new
packages are not clear.
2020-03-19 14:28:05 +02:00
Laszlo Nagy 4e191e7ac2 ad_ip_jesd204_tpl_dac: fix GUI and FPGA info population 2020-03-10 18:33:29 +02:00
Laszlo Nagy 557a72e35e ad_ip_jesd204_tpl_adc: fix GUI and FPGA info population 2020-03-10 18:33:29 +02:00
Laszlo Nagy 1b0a47c101 jesd204_rx: fix critical warning for undriven input 2020-03-10 18:17:56 +02:00
Laszlo Nagy 8af5f65ff2 util_adxcvr: enable EyeScan for GTY4 2020-03-10 18:17:38 +02:00
AndreiGrozav e1353d5291 m2k: use DMA streaming interface
The previous mechanism was "probing" the DMAs for valid data. Better said,
each interpolation channel enabled it's DMA until a valid data was received,
then it disabled the DMA read and waited for the adjacent channel(DMA) to
receive a valid data. Only when for both channels had valid data on the
DMAs interfaces was the transmission started. This added an undesired and
redundant complexity to the interpolation channels. Furthermore, for continuous
transmission, using the above mechanism lead to a fixed phase(sample)
shift between the two channels at each start.

By using the streaming mechanism the interface is simplified and the
above problems are solved.
2020-03-06 15:57:43 +02:00
Laszlo Nagy 1e11dc4e54 alt_serdes : add non DPA mode support
Due physical constraints in some cases the DPA can't be used. This
change allows the usage of input serdes on non-DPA mode.
2020-02-24 11:31:01 +02:00
Laszlo Nagy 00166d86b5 axi_ad9361 : add non DPA mode support
For Intel projects:
In cases where the clock of source synchronous interface is not routed
through a clock capable pin the DPA receive mode can't be used. Instead
the clock will be routed through a clock buffer from an IO to the clock
tree and from there to the IOPLL.
2020-02-24 11:31:01 +02:00
Laszlo Nagy 0a34f82c20 axi_ad9361/axi_ad9361_hw.tcl: fix Arria 10 fpga selection 2020-02-24 11:31:01 +02:00
Adrian Costina 0d4aa7c01e axi_dacfifo: Allow datawidths larger than the AXI datawidth 2020-02-18 11:19:02 +02:00
Arpadi 74fc68d4c3 axi_fan_control: Changed temperature thresholds to registers
implemented mux for temp reading either from internal or external
source; updated regmap; added param to identify source for temp
information; updated tacho measurements; added AVG_POW param used
for tacho measuremet average useful for simulations; defaults for
tacho measurements changed to params and added registers; added
prescaler for fsm control, FSM updated; changed register write
process; connected INTERNAL_SYSMONE to regmap, value can now be
read by software;
2020-02-14 11:21:12 +02:00
Laszlo Nagy ea06fcd7b6 util_adxcvr: add GTY4 parameters for 15.5Gbps lanerate 2020-02-10 09:48:17 +02:00
Laszlo Nagy 253b1149ad library/xilinx/util_adxcvr: merge GTY and GTH prefixed parameter
parameters with same names were duplicated with transceiver specific
names due different default values.
This does not scales very well.

Use same name for the parameters as for other parameters and do the
default value handling in the IP configuration layer.
2020-02-10 09:48:17 +02:00
Laszlo Nagy 9cce513645 jesd204/axi_jesd204_tx: Update version 2020-02-10 09:47:07 +02:00
Laszlo Nagy b8e1daa22b jesd204/axi_jesd204_rx: Update version 2020-02-10 09:47:07 +02:00
Laszlo Nagy 587a3c1a8d scripts/jesd204.tcl: Added 64b mode to Rx scripting 2020-02-10 09:47:07 +02:00
Laszlo Nagy 72186324f3 tb/loopback_64b_tb: Testbench for 64b mode
Data integrity check over a loopbacked link.
2020-02-10 09:47:07 +02:00
Laszlo Nagy bd9836886f jesd204_rx_static_config: Added 64b mode to Rx static config 2020-02-10 09:47:07 +02:00
Laszlo Nagy c3afbbc8a8 jesd204/interfaces: Added 64b mode Rx signals 2020-02-10 09:47:07 +02:00
Laszlo Nagy 7cad1f81d9 axi_jesd204_rx: Added 64b mode 2020-02-10 09:47:07 +02:00
Laszlo Nagy d1072847df jesd204_rx: 64b mode support for receive peripheral
Instantiate 64B/66B decoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
Laszlo Nagy 075f703443 jesd204_tx_static_config: Added 64b mode Tx static config 2020-02-10 09:47:07 +02:00
Laszlo Nagy e2d12a5b53 jesd204/scripts: Add 64b mode to Tx scripting 2020-02-10 09:47:07 +02:00
Laszlo Nagy c574861bf4 axi_jesd204_tx: Add 64b mode for control interface 2020-02-10 09:47:07 +02:00
Laszlo Nagy d9a31e8d83 jesd204_tx: Support for 64b mode in transmit peripheral
Instantiate 64B/66B mode encoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
Laszlo Nagy b40e055ebe jesd204/jesd204_common/jesd204_lmfc: Add multiblock clock edge, EoEMB 2020-02-10 09:47:07 +02:00
Laszlo Nagy 72e9a563da jesd204_common: Added JESD204C components 2020-02-10 09:47:07 +02:00
Laszlo Nagy 20ae7a8f7d jesd204: CRC12 component
The component can be used in Tx to compute CRC on the data to be send as
in the Rx side to compute CRC on the received data.
2020-02-10 09:47:07 +02:00
Laszlo Nagy a5346412d1 jesd204: Scrambler for 64b mode
The component can be used for scrambling in Tx and descrambling on the
Rx side of the JESD link.
2020-02-10 09:47:07 +02:00
Laszlo Nagy 474e07e579 jesd204: Add parameter for TPL data width 2020-02-10 09:47:07 +02:00
Laszlo Nagy f2060e27be jesd204_tx: add output pipeline stage
In order to help timing closure on multi SLR FPGAs add a pipeline stage
between the link layer and physical layer. This will add a fixed amount
of delay to the overall latency.
2020-02-07 09:02:46 +02:00
Arpadi 80a77b1e1b ad_rst_constr: Added the quiet option
critical warnings were caused by this file when the ad_rst.v instantiation
was done using generate depending on a parameter (i.e. axi_spi_engine)
2020-01-20 15:26:48 +02:00
Sergiu Arpadi 18a8ef8ad5 axi_generic_adc: Added constraints to ip
ad_rst.v module was missing the xdc
2020-01-17 16:46:31 +02:00
Arpadi ca623e4845 axi_laser_driver: Fixed reorder issue in ip tcl 2020-01-13 12:25:23 +02:00
Arpadi e6aa3a3b38 axi_ad9361: Fixed reorder issue in ip tcl 2020-01-13 12:25:23 +02:00
sarpadi afb28280c2 axi_gpreg: added constraints for clock_mon module 2020-01-13 12:25:23 +02:00
Istvan Csomortani 9caaba54d3 ad_mem_asym: Force the Xilinx synthesizer to infer Block RAMs 2020-01-13 12:25:23 +02:00
Arpadi 53cb087b9c ad_rst_constr: changed hier to hierarchical 2020-01-13 12:25:23 +02:00
Istvan Csomortani f07652ab5a axi_spi_engine: Add constraint for reset synchronizer 2020-01-13 12:25:23 +02:00
Istvan Csomortani d2d7f2a3f9 up_clk_mon_constr: -heir is deprecated, use hierarchical instead 2020-01-13 12:25:23 +02:00
Istvan Csomortani 4511f731af axi_laser_driver: Fix ip.tcl file
- Add a missing contraint file
  - Fix the path of the ttclk file
2020-01-13 12:25:23 +02:00
Istvan Csomortani 87a752e242 ad_rst_constr: Search pin in all hierarchy 2020-01-13 12:25:23 +02:00
Istvan Csomortani adfeb435a4 scripts: Update Vivado version to 2019.1 2020-01-13 12:25:23 +02:00
Arpadi 25816ac1b3 adi_project_xilinx: removed set_property SCOPED_TO_REF 2020-01-13 12:25:23 +02:00
Laszlo Nagy c684c2cbd6 scripts/adi_ip_xilinx.tcl: add variable width for multi bus interfaces
Bus sizes often depend on parameters. In such cases the physical indexes
of the interfaces from the multi bus must be calculated based on parameters.
For each interface expose the formula that calculates the indexes to the
block design.
2020-01-13 09:55:25 +02:00
cycollineau b93c1e6e90 intel/adi_jesd204: add bonded clock network support (#408)
* jesd204b: add bonding clocks feature (fix for some routing issues)

* intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6

* intel/adi_jesd204: clock network option renamed according to intel documentation

* intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode

Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 17:45:32 +02:00
Arpadi 3235c9189c axi_xcvrlb: added new parameters to IP
added PLL locked reg to axi regmap; IP now recognizez xcvr type
automatically
2020-01-07 16:18:33 +02:00
Laszlo Nagy 9180d4dd39 library/axi_clkgen: Fix second clock output
A typo prevents the usage of second clock output.
2020-01-07 13:21:00 +02:00
Laszlo Nagy a25323b246 util_adcfifo: fix read pointer
Read pointer should be always behind the write pointer except when it
reaches the last memory location where the writer stops.
2019-12-03 17:27:29 +02:00
Laszlo Nagy e6d63ec50d util_pack: Initital support for 32 channels 2019-11-28 16:17:58 +02:00
Laszlo Nagy 7612b5d8dd scripts/jesd204.tcl: add support for more lanes and converters for TPLs 2019-11-28 16:17:21 +02:00
Laszlo Nagy 85eabc5a08 jesd204/ad_ip_jesd204_tpl_dac: add support for more lanes and converters 2019-11-28 16:17:21 +02:00
Laszlo Nagy 002f8d8a3e jesd204/ad_ip_jesd204_tpl_adc: add support for more lanes and converters 2019-11-28 16:17:21 +02:00
Laszlo Nagy db573a59b0 jesd204: support for 16 lanes 2019-11-28 16:17:21 +02:00
AndreiGrozav cd5848976e axi_adc_trigger: Change out hold counter width
Chance out hold_counter width form 17 to 20 bits.
Out hold period max ~ 20 ms. Default out hold period 2 ms.
2019-11-26 15:15:58 +00:00
AndreiGrozav 4fdaa7fe12 axi_adc_trigger: Cosmetic change only 2019-11-26 15:15:58 +00:00
AndreiGrozav bdd44e37df axi_adc_trigger: Dynamically set the out pin hold period 2019-11-26 15:15:58 +00:00
Arpadi 4c2a539a96 axi_fan_control: Fixed ip version 2019-11-26 13:33:41 +02:00
AndreiGrozav e0813d49b6 axi_adc_trigger: Fix two sample offset
When using a non-maximum sampling rate the data is captured earlier by two
samples.
After the initial trigger jitter fix, a low latency/utilization was
desired(one sample delay for the trigger detection). After adding the
instrument trigger an equal latency between ADC and LA was required, hence the
need for a two sample delay on the trigger path. The delay was implemented
as two clock cycle delays not two sample delays.
This commit fixes this issue and offers a more robust design.
2019-11-25 13:14:18 +00:00
AndreiGrozav d844167850 axi_adc_trigger: Fix trigger jitter
A trigger jitter was added by fix on the external trigger input. It
manifests at input sampling frequencies lower than the maximum frequency.

Added the required reset and CE(valid) signal to the last output
stages of the trigger to obtain the desired functionality for all
sampling rates.
2019-11-25 13:14:18 +00:00
AndreiGrozav ecfa6bd19d axi_logic_analyzer: Add holdoff support 2019-11-25 13:14:18 +00:00
AndreiGrozav ede19a3b3d axi_adc_trigger: Add holdoff support
Add reset pin for holdoff.
2019-11-25 13:14:18 +00:00
Sergiu Arpadi 24b5de4438 sysid: Specified clock interface for input clk 2019-11-20 10:43:54 +02:00
AndreiGrozav af2f243b02 axi_dac_interpolate: Add dac trigger feature 2019-11-15 12:23:01 +00:00
Adrian Costina 39d19ef401 util_adxcvr: Add additional parameters allowing for GTH4 RX 15Gbps rates 2019-11-11 14:46:09 +02:00
AndreiGrozav 64f5a99c63 axi_adc_trigger: Add and 1 extra delay
The extra delay was added on the trigger and data paths to compensate
for the logic analyzer changes.

The extra delay will be also seen on the m2k daisy chain. The
delay between devices will be increased from 3 to 4 samples delay.
2019-10-28 13:13:10 +00:00
AndreiGrozav 10c99562cf axi_logic_analyzer: Add extra reg pipe to avoid latch 2019-10-28 13:13:10 +00:00
AndreiGrozav 6af5d3c358 axi_logic_analyzer: Improve external trigger
Fix external trigger for low sampling rates.
Because the external trigger can be a short pulse at high decimation rates
there is a high chance that the pulse will be missed.
2019-10-28 13:13:10 +00:00
Arpadi 5dc2ab9fe7 spi_engine/execution: dynamic length bugfix
ip can now send multiple words per transfer with dynamic data length
2019-10-28 12:00:23 +02:00
Istvan Csomortani 2ea8838f6a spi_engine/execution: wire/reg must be defined before usage
xsim does not like if a register or wire is used before their
definition. Make sure the every register and wire is defined before it's
used the first time.
2019-10-28 12:00:23 +02:00
Istvan Csomortani e7636f0380 axi_laser_driver: Define up_pulse_s wire in regmap 2019-10-16 15:18:43 +03:00
Istvan Csomortani 5bcaf05355 ad_ss_444to422: localparam can not be used in port definition 2019-10-16 15:18:29 +03:00
Istvan Csomortani b62aab985d ad_csc_RGB2CrYCb: localparam can not be used in port definition 2019-10-16 15:18:29 +03:00
Istvan Csomortani 1b2405a454 ad_csc_CrYCb2RGB: localparam can not be used in port definition 2019-10-16 15:18:29 +03:00
Istvan Csomortani fd74c270c5 adi_ip_xilinx: Add constraint files to constrs_1 fileset 2019-10-03 18:04:34 +03:00
Arpadi 5b79df1aa8 sys_id: version fix 2019-10-03 17:30:18 +03:00
Istvan Csomortani 97d4a14e2b util_cpack2_hw.tcl: Define allowed ranges for NUM_OF_CHANNELS
The number of channels must be round up to the closest next power of
two.
2019-10-02 15:32:17 +03:00
Istvan Csomortani acba490c2e ad_ip_jesd204_tpl_adc: BITS_PER_SAMPLE is a HDL parameter 2019-10-02 15:32:17 +03:00
Istvan Csomortani a49138c257 axi_laser_driver: Add support for Intel platforms 2019-10-02 15:32:17 +03:00
Istvan Csomortani 103cbe73dc intel/adi_jesd204: Add support for external core clock
In Subclass 1 mode, we need to use a separate clock (device clock) to
drive the link and transport layer of the interface. Implement the
required infrastructure for this scenario.

The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-10-02 15:32:17 +03:00
Istvan Csomortani aeaefd2c1c intel/jesd204_phy: Add support for external coreclkin
In Subclass 1 mode an external device clock (core clock) is used,
instead of the PCS output clock, to drive the link and transport layer.

Define an additional parameter, which can be used to enable clock input
port for the PHY module, which can be used as rx|tx_coreclkin source.
2019-10-02 15:32:17 +03:00
Istvan Csomortani 20dd17aa07 util_cpack2: Update hw.tcl file 2019-10-02 15:32:17 +03:00
StancaPop 9c9ce928d8
Merge pull request #346 from analogdevicesinc/spi_engine_trigger_update
spi_engine: Update pulse generation
2019-10-02 14:42:41 +03:00