Adrian Costina
3ea60bca5d
fmcjesdadc1: a5gt, design working with quartus 15.0
...
- added cpack to the design
- removed 166 MHz clock as it is not needed. DMA destination is 512 bits
- removed clock bridge between DMA and DDR
2015-07-23 18:11:53 +03:00
Rejeesh Kutty
d8e2196c75
fmcjesdadc1- board qsys
2015-07-22 15:44:04 -04:00
Rejeesh Kutty
d66387f482
fmcjesdadc1- board qsys
2015-07-22 15:23:39 -04:00
Rejeesh Kutty
3e2712cf18
a5gt-base: initial updates
2015-07-22 15:22:22 -04:00
Rejeesh Kutty
64070b6f27
a5gt- base system
2015-07-22 15:04:59 -04:00
Istvan Csomortani
b325c0fc01
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:22:07 +03:00
Istvan Csomortani
28aea82952
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:16:04 +03:00
Rejeesh Kutty
b4eac232db
a10gx- move cores inside qsys
2015-07-21 11:06:45 -04:00
Rejeesh Kutty
fcc298d837
a10gx- move cores inside qsys
2015-07-21 11:06:17 -04:00
Rejeesh Kutty
b3102b5095
daq2/a10gx-- xcvr+base changes
2015-07-21 11:01:45 -04:00
Rejeesh Kutty
445c4c835d
daq2-bd: xcvr components
2015-07-21 10:54:23 -04:00
Rejeesh Kutty
08e46c5ff2
a10gx-base: data-master connections
2015-07-21 10:53:54 -04:00
Rejeesh Kutty
97b8468819
daq2- constraints
2015-07-20 09:32:17 -04:00
Rejeesh Kutty
1d6a77049d
daq2- base/board split
2015-07-20 09:31:57 -04:00
Rejeesh Kutty
4b8d764852
daq2- base system modifications
2015-07-20 09:31:44 -04:00
Rejeesh Kutty
da2e7acacb
daq2- separate base/board systems
2015-07-20 09:31:15 -04:00
Rejeesh Kutty
2f53dc4412
daq2- board system only
2015-07-20 09:30:32 -04:00
Rejeesh Kutty
a87b8fbf94
a10gx- base system only
2015-07-20 09:29:30 -04:00
Rejeesh Kutty
80dc3bf92f
daq2/a10gx: remove signal tap
2015-07-16 14:59:01 -04:00
Adrian Costina
1de74c0267
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-16 18:22:05 +03:00
Adrian Costina
c949482574
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-16 18:21:49 +03:00
Adrian Costina
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
Rejeesh Kutty
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
Rejeesh Kutty
7c142178dd
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:52 -04:00
Rejeesh Kutty
ffd767deb2
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:51 -04:00
Rejeesh Kutty
6c0ad6ede8
daq3: bsplit/ccat -- removed
2015-07-15 13:05:53 -04:00
Rejeesh Kutty
a454b73d27
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:53 -04:00
Rejeesh Kutty
2d8fa2024b
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:52 -04:00
Rejeesh Kutty
226e23ca1f
fmcjesdadc1- xcvr components
2015-07-15 09:44:51 -04:00
Istvan Csomortani
3b3fe4e642
fmcomms2/FREQCVT : Update GPIOs
...
Add gpio_muxout_[tx/rx] GPIO lines and update SPI interface I/Os for the FREQCVT board
2015-07-15 15:34:45 +03:00
Istvan Csomortani
1dcbf5e5a2
fmcomms2/zc706: Fix GPIO connections
...
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
Rejeesh Kutty
1f7745610e
daq2- ddr updates
2015-07-14 12:46:52 -04:00
Istvan Csomortani
a38339a3ec
fmcomms2/rfsom: Add GPIO control for the RF card
2015-07-14 13:12:54 +03:00
Istvan Csomortani
ba2029a6e8
fmcomms2/rfsom: Delete trailing whitespaces from system_constr.xdc
2015-07-14 13:12:53 +03:00
Adrian Costina
a37932d881
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-14 11:11:33 +03:00
Rejeesh Kutty
a2e7fb9491
daq2/a10gx: qsys signal tap version
2015-07-13 10:07:18 -04:00
Rejeesh Kutty
825fddd034
transceiver split up outside qsys
2015-07-10 11:45:07 -04:00
Rejeesh Kutty
8c0d74aa90
transceiver split up outside qsys
2015-07-10 11:44:42 -04:00
Rejeesh Kutty
e40aac9ab6
transceiver split up outside qsys
2015-07-10 11:44:22 -04:00
Adrian Costina
30ea87e60b
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-09 19:55:58 +03:00
Adrian Costina
897c31ebbf
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 10:58:54 +03:00
Rejeesh Kutty
f1dd2435b4
signal tap removed
2015-07-08 15:47:31 -04:00
Rejeesh Kutty
c9e73b023d
signal tap removed
2015-07-08 15:46:52 -04:00
Rejeesh Kutty
f64df40a0a
signal tap removed
2015-07-08 15:47:50 -04:00
Rejeesh Kutty
19bf05c740
signal tap removed
2015-07-08 15:47:48 -04:00
Adrian Costina
c972779217
motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet
...
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
2015-07-08 16:23:33 +03:00
Rejeesh Kutty
bbf1c5b803
transceiver core added/gpio removed
2015-07-07 15:30:38 -04:00
Rejeesh Kutty
075b1e5424
daq2/a10gx: added axi_jesd_xcvr control
2015-07-07 10:22:36 -04:00
Istvan Csomortani
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
Istvan Csomortani
8c98399c37
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 17:48:29 +03:00
Lars-Peter Clausen
27b786e92f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
Lars-Peter Clausen
02b5ce82ad
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
Lars-Peter Clausen
281cab091c
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
Lars-Peter Clausen
5b2877b66f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
Lars-Peter Clausen
f5fc3a4d2f
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
Lars-Peter Clausen
10cc007c57
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
Istvan Csomortani
95500d4022
fmcomms2_rfsom: Fix GPIO connections
2015-07-03 13:03:19 +03:00
Istvan Csomortani
32ae7c771a
fmcomms2_ALL: Add/fix ENABLE/TXNRX control
...
Add ENABLE/TXNRX control for TDD, and preserve backward compatibility for pin control with GPIOs
2015-07-03 12:55:37 +03:00
Istvan Csomortani
5208ebedd5
Revert "fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control"
...
This reverts commit 6b15704b70
.
2015-07-03 10:20:50 +03:00
Lars-Peter Clausen
88f936cc86
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:36:51 +02:00
Lars-Peter Clausen
94d1792aba
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
.
This conflicts with moving the capture FF into the IOB.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:36:51 +02:00
Lars-Peter Clausen
eb3a0c179b
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00
Lars-Peter Clausen
e269fe1dd0
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
.
This conflicts with moving the capture FF into the IOB.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00
Rejeesh Kutty
18e8914087
fmcjesdadc1/a5gt: pn-errors version
2015-07-01 13:43:12 -04:00
Rejeesh Kutty
35aca98b5f
fmcjesdadc1/stap: added
2015-07-01 13:43:10 -04:00
Lars-Peter Clausen
68cb6df366
imageon: Connect raw data to ILA
...
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen
c8a095f79c
imageon: Increase ILA buffer size
...
2048 samples is not even enough for one 1080p line. Increase it to 4096.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen
cb18b2c0fd
imageon: Fix HDMI RX DMA data ILA probe width
...
The DMA data output of the HDMI RX core is 64-bit wide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen
c372064302
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Istvan Csomortani
6b15704b70
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
...
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 15:26:46 +03:00
Istvan Csomortani
0102e3e02c
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
...
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 13:54:01 +03:00
Lars-Peter Clausen
9e4fb2d048
imageon: Connect raw data to ILA
...
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:03:03 +02:00
Lars-Peter Clausen
e429cb3f5c
imageon: Increase ILA buffer size
...
2048 samples is not even enough for one 1080p line. Increase it to 4096.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
Lars-Peter Clausen
bcd12c8ead
imageon: Fix HDMI RX DMA data ILA probe width
...
The DMA data output of the HDMI RX core is 64-bit wide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
Rejeesh Kutty
330c205e8e
fmcjesdadc1- sys_clk changes
2015-06-30 10:47:21 -04:00
Rejeesh Kutty
6bc24e25eb
stap- need to be qsys
2015-06-29 13:26:32 -04:00
Rejeesh Kutty
d25e02d7ee
stap- need to be qsys
2015-06-29 13:26:20 -04:00
Adrian Costina
499357a65a
motcon2_fmc: Updated project to include XADC
...
- connected reset pin, as vivado reports the reset pin erroneously
- configured XADC in simultaneous sampling mode from XAUX0 and XAUX8
- connected XADC interrupt
- because in the project constraints some base pin constraints are overwritten, the project constraints are processed late
- GPI pins were assigned instead of the XADC GIO0 and GIO1, which were assigned to the XADC for external mux mode
- removed commented code
2015-06-29 16:56:25 +03:00
Istvan Csomortani
f32039f154
imageon: Hdmi_iic_rstn is accessible through a GPIO.
...
Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:49:59 +03:00
Istvan Csomortani
aef6f6b20b
imageon: Hdmi_iic_rstn is accessible through a GPIO.
...
Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:48:57 +03:00
Lars-Peter Clausen
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Adrian Costina
fcc185d769
Makefile: Updated makefiles
...
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
Rejeesh Kutty
543e08b67a
fmcadc1: sdc updates
2015-06-25 04:25:39 -04:00
Rejeesh Kutty
15740a7d34
fmcjesdadc1- 15.0 updates
2015-06-24 05:31:09 -04:00
Rejeesh Kutty
714d415804
daq2/a10gx- signaltap changes
2015-06-19 14:33:04 -04:00
Rejeesh Kutty
51e6a74a3d
daq2/a10gx- add xmit swap
2015-06-19 14:32:59 -04:00
Rejeesh Kutty
d6b1260678
daq2/a10gx- signal tap + gpio
2015-06-19 14:32:58 -04:00
Rejeesh Kutty
67df6b3ea8
a10gx- disable lab cell on dsp input register
2015-06-19 14:32:54 -04:00
Rejeesh Kutty
db76fe3298
tquest- generate the timing report file
2015-06-19 14:32:53 -04:00
Adrian Costina
c3ea99d1f8
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:31:59 +03:00
Adrian Costina
9fa705c488
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:13:02 +03:00
Adrian Costina
301226c766
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:47 +03:00
Adrian Costina
f01ba54c5f
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:33 +03:00
Adrian Costina
009d33f0a0
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:20 +03:00
Adrian Costina
41799c55dc
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:04:29 +03:00
Adrian Costina
6de154d2c2
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:04:00 +03:00
Adrian Costina
988f4fac8f
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:03:11 +03:00
Adrian Costina
e6d9735e54
fmcomms1: Fixed zed top file, the DAC dma was not correctly connected
2015-06-17 14:43:34 +03:00
Adrian Costina
2e46bda916
motcon2_fmc: Update project to use the latest util_gmii_to_rgmii
2015-06-16 17:43:10 +03:00
Adrian Costina
8fc0e0e62d
fmcjesdadc1: Fixed vc707 ethernet connections
2015-06-16 16:27:09 +03:00