cdd6c92357
xilinx/axi_adxcvr: Increase version to 17.02.a to show PRBS capability
2021-03-22 10:17:10 +02:00
5f2681314f
xilinx/axi_adxcvr/axi_adxcvr_up: Fix force error control bit
2021-03-22 10:17:10 +02:00
6f4053f3b0
util_adxcvr: Fix PRBS synchroniser typo
...
The control lines for TX PRBS must be synchronized using the TX clock.
2021-01-29 14:01:25 +02:00
14307856ea
xilinx:adxcvr: PRBS support
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The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
2021-01-12 13:40:42 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
4e438261aa
ad_serdes_out: Add CMOS support
2020-08-07 08:31:19 +03:00
837475db0d
ad_serdes_in: Add CMOS support
2020-08-07 08:31:19 +03:00
e6b9e21ad1
ad_serdes_out: Add tristate option
2020-08-07 08:31:19 +03:00
c5c772127d
up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable
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US/US+ devices have IDELAY/ODELAY with 512 taps. This requires wider
control value for delay selection. 9 bits contrary to 5 on 7series.
2020-08-07 08:31:19 +03:00
37d378c753
common/ad_serdes_out.v: Add US/US+ support
2020-08-07 08:31:19 +03:00
65d39b9164
common/ad_serdes_in.v: Add US/US+ support
2020-08-07 08:31:19 +03:00
cf145ca961
axi_adxcvr: Reset status if PLL lock is lost
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In case something happens with the reference clock of the CPLL or QPLL,
they might lose the locking. The status should reflect that.
2020-07-31 11:43:41 +03:00
32eeedb660
makefile: Update makefiles
2020-05-07 08:41:49 +01:00
8af5f65ff2
util_adxcvr: enable EyeScan for GTY4
2020-03-10 18:17:38 +02:00
0d4aa7c01e
axi_dacfifo: Allow datawidths larger than the AXI datawidth
2020-02-18 11:19:02 +02:00
ea06fcd7b6
util_adxcvr: add GTY4 parameters for 15.5Gbps lanerate
2020-02-10 09:48:17 +02:00
253b1149ad
library/xilinx/util_adxcvr: merge GTY and GTH prefixed parameter
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parameters with same names were duplicated with transceiver specific
names due different default values.
This does not scales very well.
Use same name for the parameters as for other parameters and do the
default value handling in the IP configuration layer.
2020-02-10 09:48:17 +02:00
80a77b1e1b
ad_rst_constr: Added the quiet option
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critical warnings were caused by this file when the ad_rst.v instantiation
was done using generate depending on a parameter (i.e. axi_spi_engine)
2020-01-20 15:26:48 +02:00
53cb087b9c
ad_rst_constr: changed hier to hierarchical
2020-01-13 12:25:23 +02:00
d2d7f2a3f9
up_clk_mon_constr: -heir is deprecated, use hierarchical instead
2020-01-13 12:25:23 +02:00
87a752e242
ad_rst_constr: Search pin in all hierarchy
2020-01-13 12:25:23 +02:00
3235c9189c
axi_xcvrlb: added new parameters to IP
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added PLL locked reg to axi regmap; IP now recognizez xcvr type
automatically
2020-01-07 16:18:33 +02:00
39d19ef401
util_adxcvr: Add additional parameters allowing for GTH4 RX 15Gbps rates
2019-11-11 14:46:09 +02:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
f2d2092297
axi_dacfifo: Add don't touch for the constraints to apply
2019-08-01 18:15:45 +03:00
fe09acaa2f
up_axi_update: ADDRESS_WIDTH parameter is now a localparam
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ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-26 11:58:58 +03:00
04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
b0fbe1bb57
util_clkdiv: Seperate the IP source into an intel and xilinx version
2019-06-29 06:53:51 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
81bcf9f6fc
util_adxcvr: Cleanup whitespaces for GTY4 instantiations
2019-06-25 15:35:49 +03:00
20b0c92a1f
iodelay: Expose the REFCLK_FREQUENCY parameter
2019-06-11 18:13:06 +03:00
70b7d69ff8
whitespace: Delete all trailing white spaces
2019-06-07 10:20:15 +03:00
a0d738e1a9
util_adxcvr: Add GTH parameters for line rate of 15Gbps
2019-05-24 11:05:36 +03:00
f45408d6a9
util_adxcvr: Expose GTY4 parameters required for 15Gbps link
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These parameters must be overwritten when the link is at 15Gbps.
The parameters have a GTY4_ prefix since the same parameters are shared
between GTY4 and GTH4 having different default values.
2019-05-09 15:33:15 +03:00
42d2738a30
axi/util_adxcvr: Add GTYE4 transceiver support
2019-04-12 16:19:54 +03:00
23841478c6
Remove library/scripts/common_bd.tcl
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Remove the script from the file list of the IPs that previously used it.
axi_clkgen: Add independent adi_auto_assign_device_spec proc
2019-04-09 16:07:14 +03:00
7dcaaea04e
library: Update scripts/adi_ad_ip.tcl and IPs
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Fix library makefiles dep list using generic vendor info reg
Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
2019-04-09 16:07:14 +03:00
4ae5a6d3d8
library/IPs: Auto-generate bd.tcl Update
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Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:
- axi_ad5766/axi_ad5766_ip.tcl
- axi_ad6676/axi_ad6676_ip.tcl
- axi_ad9122/axi_ad9122_ip.tcl
- axi_ad9144/axi_ad9144_ip.tcl
- axi_ad9152/axi_ad9152_ip.tcl
- axi_ad9162/axi_ad9162_ip.tcl
- axi_ad9250/axi_ad9250_ip.tcl
- axi_ad9265/axi_ad9265_ip.tcl
- axi_ad9361/axi_ad9361_ip.tcl
- axi_ad9371/axi_ad9371_ip.tcl
- axi_ad9434/axi_ad9434_ip.tcl
- axi_ad9467/axi_ad9467_ip.tcl
- axi_ad9625/axi_ad9625_ip.tcl
- axi_ad9671/axi_ad9671_ip.tcl
- axi_ad9680/axi_ad9680_ip.tcl
- axi_ad9684/axi_ad9684_ip.tcl
- axi_ad9739a/axi_ad9739a_ip.tcl
- axi_ad9963/axi_ad9963_ip.tcl
- axi_adrv9009/axi_adrv9009_ip.tcl
- axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
- axi_hdmi_tx/axi_hdmi_tx_ip.tcl
- xilinx/axi_adxcvr/Makefile
- xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
- xilinx/util_adxcvr/Makefile
- xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-30 11:26:11 +02:00
66823682b6
Add FPGA info parameters flow
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Common basic steps:
- Include/create infrastructure:
* Intel:
- require quartus::device package
- set_module_property VALIDATION_CALLBACK info_param_validate
* Xilinx
- add bd.tcl, containing init{} procedure. The init procedure will be
called when the IP will be instantiated into the block design.
- add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
- create GUI files
- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files
axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
04af519af8
axi_adxcvr: Re-indent ports
2019-03-21 14:30:39 +02:00
845c369c6b
axi_adcvr: Add initial value for reg port definition
2019-03-21 14:30:39 +02:00
8996044978
axi_adxcvr: Fix warning related to up_es_reset
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Fix the following warning:
WARNING: [Synth 8-2611] redeclaration of ANSI port up_es_reset is not allowed
Also make sure, that in all configurations, the register has a diver.
2019-03-21 14:30:39 +02:00
47f7894881
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-02-11 17:20:08 +02:00
3d7a376f8b
Makefile: update makefiles
2018-12-21 17:32:48 +02:00
a5b7699bd5
axi_adxcvr: Fix typo in initial parameters values
2018-11-16 14:18:33 +02:00
e1f15f946b
axi/util_adxcvr: Add register to control eyescan reset
2018-11-16 14:18:33 +02:00
b4ea058085
axi_adxcvr: axi_adxcvr_es.v cleanup trailing whitespaces
2018-11-16 14:18:33 +02:00
98d3d44fd1
axi_adxcvr: Fix eyescan support for ultrascale plus devices
2018-11-16 14:18:33 +02:00
251ea9471c
Remove Xilinx 6 series support
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The primitives are not used or supported by the newer versions of Vivado.
2018-10-17 10:06:40 +03:00
5b5218250b
axi_dacfifo: Move util_dacfifo_bypass module to util_dacfifo IP
2018-10-11 16:57:30 +03:00
Laszlo Nagy
Adrian Costina
Istvan Csomortani
Arpadi
AndreiGrozav