Adrian Costina
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6c6cab0e16
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fmcomms2: ZC706 modified constraints for linux build machines
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
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2014-08-01 17:34:36 +03:00 |
Istvan Csomortani
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db1c931736
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ad9625_plddr: PL DDR3 fixes
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
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2014-07-23 19:34:44 +03:00 |
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Istvan Csomortani
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2b6ce1e504
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zc706_plddr3 : Fix axi_fifo2s_axi_mrst net
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2014-07-21 15:10:36 +03:00 |
Rejeesh Kutty
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2955b9db78
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fifo2s: flush if no request, c5soc: 14.0
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2014-07-15 16:25:33 -04:00 |
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Rejeesh Kutty
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b434fe6dd5
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fmcomms5: register map changes
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2014-07-08 16:57:43 -04:00 |
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Rejeesh Kutty
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e38813fa9f
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fifo- monitor status signals
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2014-06-25 12:15:13 -04:00 |
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Rejeesh Kutty
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57bb3705f2
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zc706-plddr3: read changes to lower dma clock
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2014-06-25 09:20:58 -04:00 |
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Rejeesh Kutty
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c789dce77e
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ad9625/zc706: added pl ddr3 fifo changes
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2014-05-29 12:59:29 -04:00 |
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Rejeesh Kutty
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56ddce1e8c
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dmac: create fifo interface to avoid being treated as axi control stream
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2014-05-27 10:25:14 -04:00 |
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Rejeesh Kutty
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f73819f4d4
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zc706: pl ddr3 initial checkin
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2014-05-13 16:19:53 -04:00 |
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Rejeesh Kutty
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fbfd658f0d
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zc706: added pl ddr3 mig
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2014-04-09 15:58:12 -04:00 |
|
Istvan Csomortani
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f9a67371c0
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Zynq Base System: Reset is synchronized to lowest system clock
System reset (sys_100m_reset) is synchronized to lowest system
clock (FCLK0), via a Processor System Reset module
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2014-03-26 17:58:14 +02:00 |
|
Rejeesh Kutty
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dc44703cf1
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zynq/non-zynq: identical signal names and instances
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2014-03-17 17:02:03 -04:00 |
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Rejeesh Kutty
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a6da4ca01c
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zynq/non-zynq merge variables
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2014-03-17 16:39:52 -04:00 |
|
Rejeesh Kutty
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f3ae57a53e
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global clock and reset names
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2014-03-11 09:57:59 -04:00 |
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Rejeesh Kutty
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ddac1a8834
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added common board files
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2014-02-28 21:17:01 -05:00 |