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2336 Commits (76620bc890dfaed107dcce973df416b848370035)

Author SHA1 Message Date
Istvan Csomortani 76620bc890 avl_adxcvr: Rename variables with alt_* pre-fix 
- alt_sys_clk -> sys_clk
  - alt_xcvr_rst -> xcvr_rst
  - alt_ref_clk -> ref_clk
  - alt_fpll_rst_cntrol -> fpll_rst_control
  - alt_core_pll -> core_pll
  - alt_core_clk -> core_clk
  - alt_rst_cntrol -> rst_control
  - alt_lane_pll -> lane_pll
  - alt_ip -> jesd204_ip
  - alt_xphy -> avl_xphy
  - alt_phy_* -> phy_*
 2019-06-29 06:53:51 +03:00
Istvan Csomortani 6a42f54b1e axi_ad9361/intel: Rename varibles with alt_* pre-fix 2019-06-29 06:53:51 +03:00
Istvan Csomortani 0f7a3b953a scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
Istvan Csomortani 04ce10a570 cosmetics: Change Altera to Intel in comments 2019-06-29 06:53:51 +03:00
Istvan Csomortani 2f0dbe6151 intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym 2019-06-29 06:53:51 +03:00
Istvan Csomortani 1e074726db intel_serde: Rename alt_serdes to intel_serdes 2019-06-29 06:53:51 +03:00
Istvan Csomortani b0fbe1bb57 util_clkdiv: Seperate the IP source into an intel and xilinx version 2019-06-29 06:53:51 +03:00
Istvan Csomortani 84bd50d437 alt_ifconv: Remove unused IP 2019-06-29 06:53:51 +03:00
Istvan Csomortani d5e5fcf17a alt_mul: Remove unused IP 2019-06-29 06:53:51 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Istvan Csomortani d79fa179a3 spi_engine: Fix sync_bit instances 2019-06-28 11:18:29 +03:00
Sergiu Arpadi ba4a915af0 ad40xx/zed: fixed system_bd 
spi_engine_execution: fixed sdo default
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 42b14f341a axi_spi_engine: Generate false paths only on ASYNC_CLK mode 2019-06-28 11:18:29 +03:00
Istvan Csomortani f4de1fecdc spi_engine_execution: Add an additional register stage for the physical SPI 
The main reason is to improve timing when the SPI clock is more than
50 MHz. (the SPI Engine's spi_clk is more than 100MHz)
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 77ffa1f8ac util_dec256sinc24b: Fix the accumulator 
Do a similar fix as for the decimation stage. (ab2788)
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 158b018f58 spi_execution: Improve timing by defining resets for the shift registers 2019-06-28 11:18:29 +03:00
Istvan Csomortani d802ece39e spi_engine: Reindent execution module source code 2019-06-28 11:18:29 +03:00
Istvan Csomortani 9ab88f1200 ad40xx: Initial commit 2019-06-28 11:18:29 +03:00
Istvan Csomortani 94f8d1b424 util_axis_upscale: Sign extension must be done separately for each channel 2019-06-28 11:18:29 +03:00
Istvan Csomortani 5f8269da03 spi_egine: Add a new register for dynamic transfer length configuration 2019-06-28 11:18:29 +03:00
Istvan Csomortani 40fbb37d6f spi_engine: Add additional synchronization FIFO's to axi_spi_engine 
Add additional synchronization FIFOs to several interfaces of the
axi_spi_engine module, to prevent metastability and timing issues in
case when the system clock and the SPI clock are asynchronous.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 91801bfe0d spi_engine: Update the ad_rst instance 2019-06-28 11:18:29 +03:00
Istvan Csomortani 68c1f92066 spi_engine: Add a CDC fifo for the SYNC interface too 2019-06-28 11:18:29 +03:00
Istvan Csomortani a19f6197cc spi_engine: Fix indentation of axi_spi_engine.v 2019-06-28 11:18:29 +03:00
Istvan Csomortani b81c8373e5 spi_engine: In read only mode SDO line should stay in its default level 2019-06-28 11:18:29 +03:00
Istvan Csomortani 85bbf95c57 spi_engine/offload: SDI_READY should be asserted while offload is inactive 2019-06-28 11:18:29 +03:00
Istvan Csomortani 746f457ef9 spi_engine: Software reset should reset the offload control registers too 2019-06-28 11:18:29 +03:00
Istvan Csomortani 19655b8092 spi_engine: Define SDO default state 
There are devices where the SDO default state, between transactions, is
not GND, rather VCC.

Define a parameter, which can be used to set the default state of the
SDO line.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 45a08a004d spi_engine:execution: Set default SDI driver value for all ports 2019-06-28 11:18:29 +03:00
Istvan Csomortani 8fb6fb329e util_dec256sinc24b: Fix the differentiator 
Move the subtraction outside of the always block. In this way we're not adding
an additional delay element on to the output of the differentiator,
which brakes the transfer function of the filter.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani a15afa6c03 util_dec256sinc24b: Avoid generated clock from logic 
Do not use word_clk, create a clock enable signal instead.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 59ce663479 util_dec256sinc24b: Fix resets 2019-06-28 11:18:29 +03:00
Istvan Csomortani 6668accc96 ad7405 : Initial commit 
This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 65fea6c4c0 ad_ip_jesd204_tpl_dac: Fix up_axi instantiation 
This patch will fix the following warning:

[Synth 8-689] width (16) of port connection 'up_axi_awaddr'
does not match port width (12) of module 'up_axi'
 2019-06-27 13:47:00 +03:00
Laszlo Nagy acf6d618dd util_clkdiv: fix for multiple instances 
Vivado propagates and auto derives the clocks, however if multiple
instances of this components are used the names of the propagated clock
change while the constraint file has fixed name which will match only
the clocks from the first instance letting the second instance of the
clock div without exception.
 2019-06-27 10:33:51 +03:00
Laszlo Nagy fd6a395347 axi_fmcadc5_sync: rename generated spi clock 
Rename the clock so it won't conflict with the main spi clock name.
 2019-06-26 16:10:07 +03:00
AndreiGrozav 1c99fde06b axi_ad9361: Fix Intel interface - technology encoding update 2019-06-25 15:40:51 +03:00
AndreiGrozav 01081c93e8 axi_ad9361: Fix the interface for Intel devices 
Use missing MIMO_ENABLE parameter, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
 2019-06-25 15:40:51 +03:00
Adrian Costina 81bcf9f6fc util_adxcvr: Cleanup whitespaces for GTY4 instantiations 2019-06-25 15:35:49 +03:00
Sergiu Arpadi 369974f2e7 axi_fan_control: updated ip 
fixed tacho evaluation bug; updated fsm;
 2019-06-14 17:08:38 +03:00
Istvan Csomortani 92a0e8eb1e util_adcfifo: Fix SDC cosntraints 2019-06-13 10:59:43 +03:00
Istvan Csomortani 78b14f9803 axi_ad9625: Fix the interface instance 
The axi_ad9625_if does not have a DELAY_REFCLK_FREQUENCY parameter.
 2019-06-13 10:59:43 +03:00
Istvan Csomortani 20b0c92a1f iodelay: Expose the REFCLK_FREQUENCY parameter 2019-06-11 18:13:06 +03:00
Istvan Csomortani c4c87c7c7a axi_ad9361: Fix the _hw.tcl script 
This will fix an error introduced by 48d2c9d3 "axi_ad9361: Define a MIMO enabled
parameter"
 2019-06-11 12:39:20 +01:00
Istvan Csomortani 93b2254ff5 axi_ad9361: Fix for 'Define a MIMO enabled parameter' 2019-06-10 14:48:17 +01:00
Istvan Csomortani 48d2c9d36f axi_ad9361: Define a MIMO enabled parameter 
Define a MIMO_ENABLE parameter for the core, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
 2019-06-10 15:16:47 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Laszlo Nagy 90f9b2c36a avl_dacfifo: add missing constraint 2019-06-06 11:45:05 +03:00