Commit Graph

18 Commits (751bdd6cfc98c9e5fada8ca4b1f9042b2e2d65dc)

Author SHA1 Message Date
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Adrian Costina a49eb5853b ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
Adrian Costina 6c6cab0e16 fmcomms2: ZC706 modified constraints for linux build machines
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
2014-08-01 17:34:36 +03:00
Istvan Csomortani db1c931736 ad9625_plddr: PL DDR3 fixes
- Modified the axi slave interface handler
  - Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
Istvan Csomortani 2b6ce1e504 zc706_plddr3 : Fix axi_fifo2s_axi_mrst net 2014-07-21 15:10:36 +03:00
Rejeesh Kutty 2955b9db78 fifo2s: flush if no request, c5soc: 14.0 2014-07-15 16:25:33 -04:00
Rejeesh Kutty b434fe6dd5 fmcomms5: register map changes 2014-07-08 16:57:43 -04:00
Rejeesh Kutty e38813fa9f fifo- monitor status signals 2014-06-25 12:15:13 -04:00
Rejeesh Kutty 57bb3705f2 zc706-plddr3: read changes to lower dma clock 2014-06-25 09:20:58 -04:00
Rejeesh Kutty c789dce77e ad9625/zc706: added pl ddr3 fifo changes 2014-05-29 12:59:29 -04:00
Rejeesh Kutty 56ddce1e8c dmac: create fifo interface to avoid being treated as axi control stream 2014-05-27 10:25:14 -04:00
Rejeesh Kutty f73819f4d4 zc706: pl ddr3 initial checkin 2014-05-13 16:19:53 -04:00
Rejeesh Kutty fbfd658f0d zc706: added pl ddr3 mig 2014-04-09 15:58:12 -04:00
Istvan Csomortani f9a67371c0 Zynq Base System: Reset is synchronized to lowest system clock
System reset (sys_100m_reset) is synchronized to lowest system
	clock (FCLK0), via a Processor System Reset module
2014-03-26 17:58:14 +02:00
Rejeesh Kutty dc44703cf1 zynq/non-zynq: identical signal names and instances 2014-03-17 17:02:03 -04:00
Rejeesh Kutty a6da4ca01c zynq/non-zynq merge variables 2014-03-17 16:39:52 -04:00
Rejeesh Kutty f3ae57a53e global clock and reset names 2014-03-11 09:57:59 -04:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00