Commit Graph

4012 Commits (7340d8aa16290ee97ff883c65dd96c7dea49ab4d)

Author SHA1 Message Date
Rejeesh Kutty eadbf9ae30 altera- remove default assignments from procedure 2017-06-05 15:25:38 -04:00
Rejeesh Kutty 0bd22e78d9 altera- adi-project-create version 2017-06-05 15:24:35 -04:00
Rejeesh Kutty 1b1c7ffa61 adi_project- altera version 2017-06-05 15:13:21 -04:00
Rejeesh Kutty 95c446a41d adi_ip- initialize xdc list when ip is created 2017-06-01 15:49:18 -04:00
Rejeesh Kutty 6a437472f2 jesd204-sub-ip- no top files 2017-06-01 15:48:48 -04:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani cb4e8f66ef axi_ad9963: Delete unused source from *_ip.tcl 2017-05-31 18:27:47 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani b6d5dbf1fc license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
Adrian Costina 3a4a91b6f1 util_extract: Estetic changes 2017-05-31 11:27:32 +03:00
Rejeesh Kutty 2d56141bbd altera- 2017-r1 16.1.2 2017-05-30 12:21:27 -04:00
Adrian Costina 7aa1673238 util_extract: Update parameter names 2017-05-29 16:04:56 +03:00
Istvan Csomortani 9bb50f9e74 license: Add few cosmetic changes to LICENSE 2017-05-29 12:09:43 +03:00
Istvan Csomortani cc5d758947 license: Update top level LICENSE file
This update reflects all the new and existed licensing terms.
2017-05-29 09:58:27 +03:00
Istvan Csomortani 9cb84456ee license: Add top level license files 2017-05-29 09:57:39 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Rejeesh Kutty aaae350b3d alt_serdes- 16.1 updates 2017-05-26 11:00:07 -04:00
Rejeesh Kutty 25e42c49d6 library: move alt cores to common 2017-05-26 10:51:25 -04:00
Rejeesh Kutty ff037c0286 altera 16.1 ip changes 2017-05-26 10:48:00 -04:00
Rejeesh Kutty 097924b95d altera 16.1 ip changes 2017-05-26 10:46:28 -04:00
Istvan Csomortani 669e0a01d0 fmcomms2/a10gx: Remove project 2017-05-26 17:05:55 +03:00
Istvan Csomortani 3c47d00a96 daq1/a10gx: Remove project 2017-05-26 17:05:28 +03:00
Istvan Csomortani 414943db4b m2k: Fix Make files 2017-05-26 09:54:08 +03:00
Istvan Csomortani c4fa41e4e5 adrv9364z7020: Update README 2017-05-25 17:47:58 +03:00
Istvan Csomortani 3af00dc520 adrv9361z7035: Update README 2017-05-25 17:47:19 +03:00
Istvan Csomortani 9ecfcce4ec adrv9364z7020: Rename pzsdr1 to adrv9364z7020 2017-05-25 17:20:23 +03:00
Istvan Csomortani 26822af7e1 adrv9361z7035: Rename pzsdr2 to adrv9361z7035 2017-05-25 17:17:54 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Istvan Csomortani 10898d6618 constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
Istvan Csomortani cb8d6830f5 avl_dacfifo: Update constraints 2017-05-25 15:12:16 +03:00
Istvan Csomortani 3ee7ed7375 avl_dacfifo: Cosmetic changes 2017-05-25 15:12:15 +03:00
Istvan Csomortani 154e936a4b avl_dacfifo: Fix issues with avl_dacfifo_wr
+ fix issues with the last partial avalon transfer.
 + fix reset related problems
2017-05-25 15:12:15 +03:00
Istvan Csomortani e34e87e7f8 avl_dacfifo: Add support for partial avalon transfers
By adding support for partial avalon transfers (data width < bus width),
valid data set size (DMA transfer length) will be dependent on the DMA bus
width only.
2017-05-25 15:12:15 +03:00
Istvan Csomortani a993eefe57 avl_dacfifo: Grey coder/decoder integration 2017-05-25 15:12:14 +03:00
Istvan Csomortani 0bf6a37bd0 common: Add grey coder and decoder modules 2017-05-25 15:12:14 +03:00
Istvan Csomortani 14a058195d avl_dacfifo: Add avl_dacfifo_byteenable_coder
Define and integrate avl_dacfifo_byteenabke_coder module,
which generates the byteenable signal for the avalon interface.
2017-05-25 15:12:14 +03:00
Istvan Csomortani 81fa65cd51 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
+ avl_write_transfer_done_s is a redundant net
 + specify the net state explicitly on if statements
 + to define the edge of avl_mem_fetch_wr_address signal,
its register and its second sync register should be used
2017-05-25 15:12:13 +03:00
Istvan Csomortani 398619d866 avl_dacfifo: Add support for MEM_RATIO 32 2017-05-25 15:12:13 +03:00
Istvan Csomortani a1539a62b7 avl_dacfifo: Integrate util_delay into dac_xfer_out path
The ad_mem_asym memory read interface has a 3 clock cycle delay, from the
moment of the address change until a valid data arrives on the bus;
because the dac_xfer_out is going to validate the outgoing samples (in conjunction
with the DAC VALID, which is free a running signal), this module will compensate
this delay, to prevent duplicated samples in the beginning of the
transaction.
2017-05-25 15:12:13 +03:00
Istvan Csomortani 6d52034abb avl_dacfifo: dma_ready was muxed incorrectly 2017-05-25 15:12:12 +03:00
Istvan Csomortani da68705fee avl_dacfifo: Fix the avalon address switch 2017-05-25 15:12:12 +03:00
Istvan Csomortani 04f397f688 avl_dacfifo: Fix a few control signals
+ avl_last_transfer depends on the avl_xfer_req state
  + avl_xfer_req will be asserted after the last avalon write
transfer
2017-05-25 15:12:12 +03:00
Istvan Csomortani 8f9cadb017 avl_dacfifo: Fix the avl_write generation
The asymetric memory has a 3 clock cycle delay on its read
interface, therefor the minimum distance between two consecutive
avalon write should be 3.
2017-05-25 15:12:11 +03:00
Istvan Csomortani 0f1e51ac98 avl_dacfifo: Fix alv_mem_readen generation 2017-05-25 15:12:11 +03:00
Istvan Csomortani f456ebc6f0 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
+ all net names should have a *_s postfix
  + avl_burstcount is a constant 1, no need for an additional
register for it
  + all CDC should have two synchronization register, add
avl_last_beat_req_m2
2017-05-25 15:12:11 +03:00
Istvan Csomortani 6ea87d094e util_delay: Initial commit
Generic module to introduce a fix N cycle delay into a datapath.
2017-05-25 15:12:10 +03:00
Istvan Csomortani 9a6dc36289 avl_dacfifo: Fix indentation for acl_dacfifo.v 2017-05-25 15:12:10 +03:00
Istvan Csomortani 7666c9f0d2 avl_dacfifo: Add a parameter AVL_ADDRESS_WIDTH 2017-05-25 15:12:10 +03:00
Istvan Csomortani 6dbbe2f1ca altera/ad_mem_asym: Fix grounded bus for marco instance
The "'b0" constant will be translate as a 32 bit width vector by
ModelSim, and will throw a buswidth mismatch error. Tie the data_b
bus to zero, using its width parameter.
2017-05-25 15:12:09 +03:00
Lars-Peter Clausen d883aabcc1 adi_ip.tcl: Use analog.com for interface vendor
Currently the scripts use 'analog.com' as the vendor property for IP cores,
but 'ADI' for interfaces.

Make things consistent by using 'analog.com' for both interfaces as well
as IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:10:15 +02:00