zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
5,907 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

17 Commits (703cc8a17ebe27715c4b87279bbd31412ec10cf3)

Author SHA1 Message Date
Laszlo Nagy dafdd1c1e9 ad9208_dual_ebz: Use ad_xcvrcon procedure to connect device clock 2021-02-05 15:24:15 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Laszlo Nagy 10a808b504 ad9208_dual_ebz/vcu118: remove GTY prefix from parameters 2020-02-10 09:48:17 +02:00
StancaPop 05c20af988
Merge pull request #430 from analogdevicesinc/update_tcl 
Rename projects for consistency
 2020-02-06 16:32:40 +02:00
Laszlo Nagy 7c3b4a5c73 ad9208_dual_ebz: Cleanup workarounds 
Cleanup placement constraints and let the tool have more freedom to
place and route the design. This is possible only after balancing the
memory and system clocks.
 2019-09-16 10:00:14 +03:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 2019-06-11 18:13:06 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Istvan Csomortani 6cac0b9917 makefile: Update dual_ad9208 2019-05-29 10:23:24 +03:00
Laszlo Nagy 607f2bd8de ad9208_dual_ebz: Initial version 
This commit add support for the dual AD9208-DUAL-EBZ board.

The clocking scheme is different from the other projects.
The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK),
it is received directly from the clockchip  SCLKOUT9 output through the REFCLK1.
This is needed for deterministic latency where SYSREF must be sampled
with the device clock by meeting setup and hold time.

The two channels from each converter are merged together and transferred  to the DDR with a single DMA.

It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL.

REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC
board.
 2019-05-16 13:29:34 +03:00