d4c393332a
ad_ip_jesd204_tpl: TPL has and address space of 4KB
2020-05-25 11:55:40 +03:00
bff8a9fafb
scripts/jesd204.tcl: rename tpl core instance
...
Having the same name for dac and adc TPLs creates conflict in the
address segment naming having random names associated to the segments.
This causes difficulties during scripting of the project in test bench
mode.
2020-05-20 19:08:25 +03:00
10c9f7a70d
ad_ip_jesd204_tpl_dac: Add option for an external synchronization pin
...
The external synchronization signal should be synchronous with the
dac clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received
Added EXT_SYNC parameter to be able to keep the dac_sync original
behavior
2020-05-13 10:09:43 +03:00
5d4c6701d9
ad_ip_jesd204_tpl_adc: Add external synchronization
...
The external synchronization signal should be synchronous with the
adc clock. Synchronization will be done on the rising edge of the signal.
The control bit is self clearing. Status bit shows that the synchronization
is armed but the synchronization signal has not yet been received. While
the synchronization mechanism is armed, the adc_rst output signal is set
The current format should allow for the SYSREF signal to be used as
synchronous capture start, but will need to be disabled before the
synchronization mechanism is armed
2020-05-13 10:09:43 +03:00
70d139af7f
jesd204/ad_ip_jesd204_tpl_dac: Fix Intel dependencies
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Even if the IQ rotation is disabled in the projects all modules has to be
added to the list of dependencies to avoid compilation errors.
2020-04-08 10:50:28 +03:00
af060700b8
jesd204/ad_ip_jesd204_tpl_dac: add I/Q roation
2020-04-03 11:16:37 +03:00
341221dc91
jesd204: Update jesd204_tx_lane.v
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Removed decoder for tx_ready.
2020-04-01 10:29:40 +03:00
4e191e7ac2
ad_ip_jesd204_tpl_dac: fix GUI and FPGA info population
2020-03-10 18:33:29 +02:00
557a72e35e
ad_ip_jesd204_tpl_adc: fix GUI and FPGA info population
2020-03-10 18:33:29 +02:00
1b0a47c101
jesd204_rx: fix critical warning for undriven input
2020-03-10 18:17:56 +02:00
9cce513645
jesd204/axi_jesd204_tx: Update version
2020-02-10 09:47:07 +02:00
b8e1daa22b
jesd204/axi_jesd204_rx: Update version
2020-02-10 09:47:07 +02:00
587a3c1a8d
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2020-02-10 09:47:07 +02:00
72186324f3
tb/loopback_64b_tb: Testbench for 64b mode
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Data integrity check over a loopbacked link.
2020-02-10 09:47:07 +02:00
bd9836886f
jesd204_rx_static_config: Added 64b mode to Rx static config
2020-02-10 09:47:07 +02:00
c3afbbc8a8
jesd204/interfaces: Added 64b mode Rx signals
2020-02-10 09:47:07 +02:00
7cad1f81d9
axi_jesd204_rx: Added 64b mode
2020-02-10 09:47:07 +02:00
d1072847df
jesd204_rx: 64b mode support for receive peripheral
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Instantiate 64B/66B decoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
075f703443
jesd204_tx_static_config: Added 64b mode Tx static config
2020-02-10 09:47:07 +02:00
e2d12a5b53
jesd204/scripts: Add 64b mode to Tx scripting
2020-02-10 09:47:07 +02:00
c574861bf4
axi_jesd204_tx: Add 64b mode for control interface
2020-02-10 09:47:07 +02:00
d9a31e8d83
jesd204_tx: Support for 64b mode in transmit peripheral
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Instantiate 64B/66B mode encoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
b40e055ebe
jesd204/jesd204_common/jesd204_lmfc: Add multiblock clock edge, EoEMB
2020-02-10 09:47:07 +02:00
72e9a563da
jesd204_common: Added JESD204C components
2020-02-10 09:47:07 +02:00
20ae7a8f7d
jesd204: CRC12 component
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The component can be used in Tx to compute CRC on the data to be send as
in the Rx side to compute CRC on the received data.
2020-02-10 09:47:07 +02:00
a5346412d1
jesd204: Scrambler for 64b mode
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The component can be used for scrambling in Tx and descrambling on the
Rx side of the JESD link.
2020-02-10 09:47:07 +02:00
474e07e579
jesd204: Add parameter for TPL data width
2020-02-10 09:47:07 +02:00
f2060e27be
jesd204_tx: add output pipeline stage
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In order to help timing closure on multi SLR FPGAs add a pipeline stage
between the link layer and physical layer. This will add a fixed amount
of delay to the overall latency.
2020-02-07 09:02:46 +02:00
7612b5d8dd
scripts/jesd204.tcl: add support for more lanes and converters for TPLs
2019-11-28 16:17:21 +02:00
85eabc5a08
jesd204/ad_ip_jesd204_tpl_dac: add support for more lanes and converters
2019-11-28 16:17:21 +02:00
002f8d8a3e
jesd204/ad_ip_jesd204_tpl_adc: add support for more lanes and converters
2019-11-28 16:17:21 +02:00
db573a59b0
jesd204: support for 16 lanes
2019-11-28 16:17:21 +02:00
acba490c2e
ad_ip_jesd204_tpl_adc: BITS_PER_SAMPLE is a HDL parameter
2019-10-02 15:32:17 +03:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
fe09acaa2f
up_axi_update: ADDRESS_WIDTH parameter is now a localparam
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ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-26 11:58:58 +03:00
0f7a3b953a
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2019-06-29 06:53:51 +03:00
04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
5329458a62
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2019-06-29 06:53:51 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
65fea6c4c0
ad_ip_jesd204_tpl_dac: Fix up_axi instantiation
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This patch will fix the following warning:
[Synth 8-689] width (16) of port connection 'up_axi_awaddr'
does not match port width (12) of module 'up_axi'
2019-06-27 13:47:00 +03:00
9832c87144
jesd204:tpl: add missing dependencies for Intel
2019-05-24 11:04:46 +03:00
157afcbc33
tb_base: Fix various test benches
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The tb_base.v verilog files does not contain a full module definition,
just some plain test code. In general the files is sourced inside the
test bench main module. As is, defining a timescale in these files will
generate an error, because timescale directive can not be inside a
module.
Delete all the timescale directive from these files.
2019-05-17 11:20:48 +03:00
b90c2e79dc
jesd204_rx: add parameter for input pipeline stages
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Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
2019-05-16 13:29:34 +03:00
92d87c2d60
jesd204/scripts: fix indentation
2019-05-16 13:22:55 +03:00
cf258ace83
jesd204/scripts: TPL add support for M=1
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When only one converter is used there is no need for concatenation and
slicer cores. In that case the TPL will connect to port 0 from the
application layer.
2019-05-16 13:22:55 +03:00
168e1951ee
library: Add `timescale to modules that are missing it
2019-05-15 15:37:44 +03:00
c32b4b02f3
sync_bits: Change I/O names of wires "in" and "out" for VHDL users
2019-04-23 18:03:23 +03:00
01748d4364
jesd204:axi_jesd204_tx: set OOC default clock constraints
2019-04-22 10:27:16 +03:00
4264a7a0dd
jesd204:axi_jesd204_rx: set OOC default clock constraints
2019-04-22 10:27:16 +03:00
Istvan Csomortani
Laszlo Nagy
Adrian Costina
Maxim
Arpadi