1766b42a93
ad_mem_asym: Add option to control cascade layout
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-15 12:27:49 +03:00
7423ecae14
data_offload: Improve external synchronization
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This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:01 +03:00
2178191610
ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine
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Memory requirements are the same as with the dacfifo (1 MiB).
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
564ef77588
data_offload: Calculate AXI_ADDRESS_LIMIT automatically
2021-08-06 11:55:24 +03:00
c82b0fb420
data_offload: Delete fifo_dst_rlast
2021-08-06 11:55:24 +03:00
703cc8a17e
data_offload_bd: Calculate the address limit from the address width
2021-08-06 11:55:24 +03:00
4c03580156
data_offload: Add integration process for Xilinx carriers
2021-08-06 11:55:24 +03:00
3c83694755
adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock
2019-12-03 17:27:56 +02:00
36a1767329
Add generic fir filters processes for RF projects
2019-08-20 16:24:47 +03:00
bed5ce516c
adcfifo/dacfifo: fix alignments
2019-01-23 14:45:45 +02:00
a3766b464b
adcfifo/dacfifo: Use proc to create infrastructure
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Create the dacfifo/adcfifo infrastructure with procedures.
This will allow moving the parameters of the dac/adcfifo inside
the block design so it can be calculated based on other parameters.
2019-01-23 14:45:45 +02:00
2535165461
xilinx- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:19 -04:00
c1aac4a9fb
common: adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
89b49d2f67
fifo- as board files
2017-02-22 15:18:50 -05:00
879ed64bb6
compression flag changes
2017-02-22 15:15:53 -05:00
754ac6a403
w/r-fifo- removed
2017-02-22 15:10:06 -05:00
8464816c82
dmafifo-split to adc/dac
2016-08-16 12:54:39 -04:00
62c7114d77
Enable bitstream compression for Xilinx projects
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Enabling bitstream compression reduces the size of the generated bitstream.
This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.
On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.
The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.
When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.
Initial tests show a reduction of a round 50% in size for most ADI
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:16:15 +02:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
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The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
6862655b0d
Add .gitattributes file
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Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
bad821ba1c
sys_dmafifo: Update the p_sys_dacfifo process
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Update the ports and parameters at util_dacfifo instantiation.
2015-05-11 12:20:47 +03:00
a100ecd308
util_dacfifo: Update BRAM DAC Fifo
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The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
4f7f109056
util_adcfifo: added
2015-04-07 16:08:38 -04:00
2302f282d3
sys_dmafifo: ad_connect updates
2015-03-09 16:06:06 -04:00
eb569b991d
dmafifo- remove util fifo setup
2015-01-06 16:23:14 -05:00
9e707d8a33
rfifo: wrapper updates
2015-01-06 16:17:33 -05:00
a944deebd5
wfifo: wrapper updates
2015-01-06 16:17:25 -05:00
cdd1408d3c
dmafifo: parameterized address width
2014-11-20 09:28:02 -05:00
074662a622
dmafifo: common interface with fifo2s
2014-11-12 15:24:31 -05:00
56859ad4c9
sys_dmafifo: use internal memory
2014-10-30 15:26:28 -04:00
4c0e4d280f
dmafifo: internal version- light duty
2014-10-30 11:12:13 -04:00
360e7104b6
dmafifo: axi version- heavy duty
2014-10-30 11:12:12 -04:00
d471b61f3e
fifo: merge zynq and non-zynq
2014-10-27 09:59:54 -04:00
5715c5b28f
dmafifo: axi stream interface
2014-10-15 14:50:57 -04:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
7b280b3bbf
fmcomms6: zc706 build-only version
2014-08-27 10:44:37 -04:00
David Winter
Istvan Csomortani
AndreiGrozav
Laszlo Nagy
Rejeesh Kutty
Lars-Peter Clausen
Adrian Costina