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Author SHA1 Message Date
Laszlo Nagy 03682f6193 projects/adrv9001/zcu102/lvds_constr.xdc: Fix timing constraints 
1. Reduce max allowed skew between source synchronous clocks that can
occur due PCB differences. 250ps represents a difference more than an
inch.

2. In order to reduce skew between source synchronous clock and the
divided clock instruct the tool to use a common clock root for them.
 2021-10-27 14:40:08 +03:00
Laszlo Nagy 72f916fcf5 adrv9001/zcu102: Update interface signal names based on direction 
Let the names of signals from source synchronous interface match the
direction of the signals.
 2020-08-28 13:23:00 +03:00
Laszlo Nagy b27f3ac18f adrv9001:zcu102: Initial version 
Generic project that supports CMOS or LVDS interface for the ADRV9001 transceiver.
 2020-08-24 17:49:12 +03:00