6b94259a52
projects/common: Add system_top _project templates
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Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct code and modify according to guidelines
* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct/Add missing wrapper ports and iobufs
* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
ac701/system_top.v: Change top based on previous projects
* Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
projects/common: Modify templates to build without errors
* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
system_project: Added adi_board, adiobuf sourcing
system_top: Removed hdmi, i2c, fanpwm, spdif ports
according to base design
* c5soc: Added version settings
Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
Removed unnecessary ports
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Delete microzed vmk_es templates
* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-20 17:00:49 +03:00
b02f437110
docs: Add common template for evaluation board specific fmc files
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Instructions to use the template are found on the first page of the template
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2022-09-20 14:11:08 +03:00
7cde7cd048
projects/scripts: Add fmc constraints generator script
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Using the script:
- make sure that the eval board in use has a common fmc connection file.
if you created a new one, it should be saved as &project_name_fmc.txt inside
&project_name/common
- open a tcl terminal, either inside or outside the project
- make sure your current directory is &hdl_repo/projects/&project_name/&carrier
- source the script found at &hdl_repo/project/scripts/fmc_constr_generator.tcl
- call gen_fmc_constr $parameter_1 $parameter_2:
- in case of only one fmc port on the carrier call without any parameters
- if there are two fmc ports on the carrier and you want to use only one,
the first parameter should contain an indication (fmc_lpc/hpc, fmc0/1, etc.)
- if there are two fmc ports on the carrier and you want to use both, then
both parameters should contain an indication
- the constraints file will be generated in the current directory
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2022-09-20 14:11:08 +03:00
72378a6d4a
projects: Add fmc connection files for eval boards
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Creating a new eval board fmc file:
- docs: Open FMC_eval_board_template.xlsx
- follow the instructions on the first sheet
2022-09-20 14:11:08 +03:00
72cf8f9b5d
projects/common: Add fmc connection files for every platform
2022-09-20 14:11:08 +03:00
158c10df34
projects: starndadize the jesd make parameters
2022-09-13 11:53:21 +03:00
b1bf17d574
scripts/check_readme: Change search to be case insensitive
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2022-09-01 13:43:25 +03:00
8905147698
common/tb/ad_pack_tb: Add non random scenario as first test for easier debug
2022-08-25 12:35:59 +03:00
d20e604864
ad9082_fmca_ebz/zcu102: Make TPL width overwritable
2022-08-25 12:35:42 +03:00
ee3af4c9c6
axi_jesd204: Cleanup unused parameter
2022-08-25 12:35:42 +03:00
a1d31b4913
axi_jesd204_rx/jesd204_up_rx: Set buffer delay in beats of device clock
2022-08-25 12:35:42 +03:00
e332409610
ad9081_fmca_ebz: Make TPL width overwritable
2022-08-25 12:35:42 +03:00
5c86c15ff3
library/jesd204: Add support for a gearbox ratio in which the TPL width is smaller than the PHY interface
2022-08-25 12:35:42 +03:00
567be16bf6
library/jesd204: Update the script which computes the TPL width to be able to assign custom values
2022-08-25 12:35:42 +03:00
5a06f186ae
ad9081_fmca_ebz/common: Use the script to compute the TPL width
2022-08-25 12:35:42 +03:00
f955fbc6c0
adi_pd.tcl: Fix sysid branch string
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For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
dev_new_device^[[m"
The above escape codes will mess up a terminals color scheme when this
information is read from sysid and displayed on a terminal.
Use --no-color flag to fix this issue.
2022-08-25 11:36:25 +03:00
388611866a
projects: Fix some Makefiles
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* ad9082_fmca_ebz/vcu118
* dac_fmc_ebz/vcu118
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-25 09:35:55 +03:00
cf4e1b79cf
scripts:adi_env: Change the default version of Quartus Standard to 21.1 ( #996 )
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New version of Quartus Standard for de10nano and sockit was changed
to 21.1.
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-08-24 17:01:06 +03:00
cc18f90579
Added axi_ad7768 IP Core ( #989 )
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* projects/ad7768evb: Initial commit with axi_ad7768 IP
* library/axi_ad7768: Initial commit for AD7768/AD7768-4
2022-08-24 16:57:14 +03:00
a824bbfdbe
library/scripts/adi_ip_xilinx.tcl: remove duplicate adi_env.tcl source
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Signed-off-by: LIacob106 <liviu.iacob@analog.com>
2022-08-23 17:55:27 +03:00
4307e3071f
scripts:adi_env: Change the default version of Quartus Pro to 21.4 ( #988 )
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New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
2022-08-18 17:08:29 +03:00
e02d31cdfd
scripts: Set required Vivado version only in adi_env.tcl
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Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
dde37124a4
scripts: Update Vivado version to 2021.2
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Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
214cf5896e
library/common: Enable automatic logging of simulation output
2022-08-10 12:00:15 +03:00
79579f65df
library/common: Update the packing IPs to be more generic
2022-08-10 12:00:15 +03:00
0595f93452
AD777x support for ZedBoard and DE10Nano ( #937 )
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* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.
* library/axi_ad777x: Initial commit for Xilinx and Intel
* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
2022-08-10 11:29:05 +03:00
ab29f21f7a
axi_ltc2387: Update data formatter instance to use bits instead of octets
2022-08-08 14:22:24 +03:00
d8a6e81c7e
jesd204/ad_ip_jesd204_tpl_adc: Fix data formater for N'=12 if DMA interface is also 12
2022-08-08 14:22:24 +03:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
929f80cd31
library/jesd204: Updated jesd to support more lanes
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Modified the maximum number of supported lanes up to 32 lanes for every JESD layer
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-08-04 13:10:53 +03:00
d48b1bcdce
ad9081_fmca_ebz/vck190: Expose ref clock parameter
2022-08-04 09:52:57 +03:00
78333b2c90
ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx
2022-08-04 09:52:57 +03:00
3379dd3bdb
ad9082_fmca_ebz/zcu102: Make JESD_MODE overwritable
2022-08-04 09:50:18 +03:00
7a48f1beb9
util_do_ram: Fix Rx path for interrupted transfers
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When capture length is not programmed the DMA will interrupt the
transfer once it received all the samples he was set in its descriptor,
this case must be handled by resetting the read process and returning
an end of transfer (eot) to the data offload control logic.
2022-08-04 09:45:52 +03:00
1d4b27ea8c
util_axis_fifo_asym: Fixes for simulation
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Initialization of regs was not executed in always(*) blocks since
the block is not triggered due missing inputs.
2022-08-04 09:45:52 +03:00
4982104982
data_offload: Fix Tx bypass
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Tx path was gated by the FSM also in bypass mode. This must be avoided
since the bypass mode should be independent of the FSM.
Write to bypass fifo only when bypass is enabled
2022-08-04 09:45:52 +03:00
54a22d036c
adi_pd.tcl: Fix git_clean_string logic
2022-08-02 17:11:49 +03:00
94c4a291a7
cn0561_coraz7s: Fix gpio connections
2022-08-02 17:11:19 +03:00
bb3027995a
sysid: Add sysid support for de10nano
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make adv7513
make 0540
2022-08-02 14:15:34 +03:00
c748b3bbc7
ad9082_fmca_ebz/zc706: Fix parameters
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Match default parameters for L=4 M=8 mode with 10Gbps.
The L=8 M=4 would require lane rate of 15Gbps that is not supported on
zc706.
2022-08-01 16:40:03 +03:00
aae7971689
ad9082_fmca_ebz/vcu118: Fix default lane rate parameter
2022-08-01 16:40:03 +03:00
aed7032e0c
ad9082_fmca_ebz/zcu102: Fix default lane rate parameter
2022-08-01 16:40:03 +03:00
bdaa0f086b
data_offload: Increase bypass FIFO size
2022-08-01 12:47:26 +03:00
2b274f945f
ad9081_fmca_ebz: Reset cpack with Rx data offload
2022-08-01 12:47:26 +03:00
d48ab915a5
vcu128: Connect sys_mb_rstgen/ext_reset_in accordingly
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Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-07-29 20:05:08 +03:00
472f41ad2c
ad_ip_jesd204_tpl_adc_hw.tcl: Add 14 bit option for converter resolution
2022-07-25 14:14:28 +03:00
6aa899f161
scripts/adi_project_xilinx.tcl: Add new constraints file support
2022-07-20 14:36:04 +03:00
9864d96096
Merge CN0506 projects into a parameterized one
2022-07-20 14:36:04 +03:00
6113f3d70f
action: Add workflow for github action to run check_guideline.py
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Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
1014a0de78
script: Add Py script to check for guideline rules & README.md
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Added readme_check_guideline.md along with the check_guideline.py
to explain the usage of this and to show how it should be used.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
laurent-19
AndrDragomir
LIacob106
Iulia Moldovan
Laszlo Nagy
Ionut Podgoreanu
AndreiGrozav
ladace
PopPaul2021
Filip Gherman
Laszlo Nagy
Sergiu Arpadi
alin724