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3397 Commits (6aadb49e80969596cb0e2db2716cdb821a8c1bdd)

Author SHA1 Message Date
Adrian Costina d010f3e687 sdrstk: Update Makefile to remove pack/cpack dependancy and add util_fir_dec/util_fir_int dependancy 2016-10-28 16:13:52 +03:00
Adrian Costina f2e12cc88f util_fir_dec: Shifted the output data to the left so that the amplitude remains 
constant
 2016-10-28 15:18:36 +03:00
Adrian Costina d9b756e7ad util_fir_int: Shifted the output data to the left so that the amplitude remains constant 2016-10-28 15:17:30 +03:00
Adrian Costina ac8a6124af sdrstk: Added interpolation and decimation filters. Removed cpack/upack 2016-10-27 19:33:28 +03:00
Adrian Costina 30314e4492 library: Added util_fir_int and util_fir_dec interpolation/decimation filters 2016-10-27 19:31:50 +03:00
Rejeesh Kutty 8107514dde altera/common- ad_serdes_clk 2016-10-27 09:41:10 -04:00
Rejeesh Kutty 50552ce7d6 adrv9371x- altera updates 2016-10-27 09:25:00 -04:00
Rejeesh Kutty f752f0c9d7 a10soc- xcvr updates 2016-10-27 09:25:00 -04:00
Rejeesh Kutty f7e3703b98 axi_ad9371- avalon-s interfaces 2016-10-27 09:25:00 -04:00
Adrian Costina d4c7b7ca57 ccusb_lvds: Fixed IIC constraints 2016-10-26 11:12:02 +03:00
Adrian Costina 6607aa707d pzsdr1: Renamed projects to have lvds/cmos sufix 2016-10-26 11:09:43 +03:00
Adrian Costina 9ff92fdf5b pzsdr: Renamed projects to have lvds/cmos sufix 2016-10-26 11:07:29 +03:00
AndreiGrozav b8363d778d arradio: Makefile update 2016-10-25 20:36:56 +03:00
AndreiGrozav 6f611e0d10 altera/alt_serdes: Add support for Cyclone V 2016-10-25 20:32:51 +03:00
AndreiGrozav 08cef5a745 axi_ad9361: Add Cyclone V SERDES support 2016-10-25 20:24:17 +03:00
Adrian Costina 138eeebc9b ccusb_lvds: Initial commit 2016-10-25 16:32:44 +03:00
Rejeesh Kutty 5731ba3300 fmcomms11- xcvr updates 2016-10-24 09:51:40 -04:00
Istvan Csomortani 7e57a89ce5 daq1: Add support for A10GX 2016-10-24 11:43:33 +03:00
Istvan Csomortani de0c487195 axi_ad9684: Add Altera support for the core 2016-10-24 11:43:22 +03:00
Istvan Csomortani 3f3606d318 axi_ad9122: Add Altera support for the core 2016-10-24 11:43:12 +03:00
Istvan Csomortani aa46de5e5e adi_ip_alt: Add ad_generate_module_inst proc 
Add a tcl process, which can be used to generate custom module
names during the generation phase. This will be used to create
different ad_serdes_clk module, in case when independent IOPLLs are
needed for TX and RX.
 2016-10-24 11:43:00 +03:00
Istvan Csomortani 707038937a alt_serdes: Add additional parameters 
Add additional parameters to keep the top of ad_serdes_* modules
consistant through differente carriers.
 2016-10-24 11:42:43 +03:00
Rejeesh Kutty c9ac870086 usrpe31x- updates 2016-10-21 13:59:43 -04:00
Rejeesh Kutty 7b958fed87 hdlmake- updates 2016-10-21 13:59:43 -04:00
Rejeesh Kutty 48e90f0e9b usrpe31x- added 2016-10-21 13:59:43 -04:00
Istvan Csomortani 8dbfe9258f axi_ad9162: Delete duplicated port 2016-10-21 13:47:01 +03:00
Istvan Csomortani 801f980aeb adrv9371: Fix parameter name 2016-10-21 12:50:20 +03:00
Istvan Csomortani 3abd87631a fmcomms11: Fix parameter name 2016-10-21 12:49:48 +03:00
Rejeesh Kutty 0beecea02d util_adxcvr- ultrascale updates 2016-10-19 13:06:10 -04:00
Rejeesh Kutty 7db0c03a92 pzsdr1+ccbox -- updates 2016-10-19 10:32:28 -04:00
Lars-Peter Clausen 72c05e8635 axi_dmac: Fix constraints for ultrascale 
Replace "PRIMITIVE_SUBGROUP == flop" with "IS_SEQUENTIAL" as the former is
series7 specific while the later works on all platforms. This fixes the
axi_dmac timing constraints for ultrascale based platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-10-19 14:00:54 +02:00
Adrian Costina c1b7c5e77a usb_fx3: Added FIFO on the FX3 to Zynq path, between FX3 core and DMA core 2016-10-19 09:30:51 +03:00
AndreiGrozav 17cfdd6be9 fmcomms2/a10gx: Update Makefile and qsys script 2016-10-18 12:42:14 +03:00
Istvan Csomortani ecc0addb8c scripts/adi_ip_alt.tcl: Script is case insensitive for its arguments 2016-10-18 11:25:06 +03:00
Rejeesh Kutty 918ce45e2a pzsdr1/ccbox- updates 2016-10-17 16:29:57 -04:00
Rejeesh Kutty cb97bc500a hdlmake updates 2016-10-17 16:29:57 -04:00
Rejeesh Kutty 950acaed15 ccbox- copy 2016-10-17 16:29:57 -04:00
Rejeesh Kutty bf949f1a88 axi_xcvrlb- xcvr updates 2016-10-17 16:16:57 -04:00
Rejeesh Kutty 1b3fcb5863 util_adxcvr- parameter defaults 2016-10-17 16:10:57 -04:00
Adrian Costina 7c541c704a usdrx1: ZC706, Update project to the new GT framework 2016-10-14 18:08:08 +03:00
Adrian Costina 1d1fe26624 fmcomms7: ZC706, Update project to new GT framework 2016-10-14 17:32:23 +03:00
AndreiGrozav a026d44435 axi_generic_adc: Add missing up_adc_common connections 2016-10-12 13:20:26 +03:00
AndreiGrozav b543402051 axi_mc_current_monitor: Add missing up_axi connection 2016-10-12 13:20:26 +03:00
AndreiGrozav 91995c082d axi_ad9684: Fixed up_drp_*data width 2016-10-12 13:20:26 +03:00
AndreiGrozav a505d304af Add up_dac_common missing connections 2016-10-12 13:20:26 +03:00
AndreiGrozav 43ee917d53 Add up_dac_channel missing connections 2016-10-12 13:20:26 +03:00
AndreiGrozav 1131be91ed axi_ad9361: Makefile update 2016-10-11 23:34:13 +03:00
AndreiGrozav b7767aa18f xilinx/axi_ad9361_lvds_if: Remove ila 2016-10-11 18:13:45 +03:00
AndreiGrozav 2d93d787ab altera/ad_cdfilter: Update interface to Verilog 2001 standard 2016-10-11 17:59:21 +03:00
AndreiGrozav 369dad60b0 axi_ad9361: Add Altera SERDES interface support 2016-10-11 17:59:19 +03:00