001e7a52b1
util_adxcvr: Add LANE_RATE parameter so it can be used for automatic constraint generation
...
Add separate LANE_RATE for TX and RX
2021-05-14 15:39:40 +03:00
cb5e66ff9c
xilinx/util_adxcvr: 204C link support for GTY4
...
Set channel parameters based on link mode (1 - 204b or 2 - 204c).
2021-05-14 15:39:40 +03:00
2d13b5b8cd
xilinx/axi_adxcvr: Add 204C support, increase version to 17.3.a
2021-05-14 15:39:40 +03:00
77a5edaa83
scripts/adi_board.tcl: In 204C do not connect SYNC
...
Take link mode parameter from util_adxcvr, check it against the axi_adxcvr.
2021-05-14 15:39:40 +03:00
60612720cd
jesd204/jesd204_common/sync_header_align: Initial version
...
This module creates sync header alignment described in section 7.6.1 of
the JESD 204C specification.
The alignment relies on the bitslip capability of the connected
transceiver.
2021-05-14 15:39:40 +03:00
0c0c6843e3
jesd204/axi_jesd204: Complete clock definitions in out of context mode
2021-05-14 15:39:40 +03:00
e08ca2fc20
jesd204: Add out of context constraint file for link layer cores
...
For the out of context flow it is important to have all clocks defined
at the interface, especially if the clock are used in the other constraints.
2021-05-14 15:39:40 +03:00
b4c5031272
axi_pulse_gen: Fix typo introduced in c235e5e58
2021-05-10 13:26:30 +03:00
37238916df
Testbenches: Unify and optimize HDL testbenches
...
Create a common 'run_tb.sh' script to be called by every testbench.
Unify file and testbenches names.
Fix util_pack/cpack_tb.
Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui)
Add ascript for that generates output in xml format (used by CI tools).
2021-05-07 19:53:14 +03:00
c235e5e583
axi_pwm_gen: Initial commit
...
axi_pwm_gen is based on util_pulse_gen, it introduces the option of
phase option between pulses(PWMs) and external synchronization.
Documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-05-07 19:09:32 +03:00
1db04a47b8
ad9083_evb: Update parameters to 10Gpbs lane rate
2021-04-19 13:21:34 +03:00
8335e1bd9a
sysid: Make sure gitbranch_string is always declared
...
Parsing of not existed "gitbranch_string" fails the build process.
2021-03-24 13:34:32 +02:00
6a374ef457
ad469x/zed: Add multicycle path constraint
2021-03-22 13:05:05 +02:00
9413afa41c
jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg
...
get_cell on i_lmfc/cdc_sync_stage1_reg doesn't return anything because design was updated.
This generates a CRITICAL WARNING and since the constraint it not necessary anymore, it can be deleted.
2021-03-22 10:55:00 +02:00
cdd6c92357
xilinx/axi_adxcvr: Increase version to 17.02.a to show PRBS capability
2021-03-22 10:17:10 +02:00
5f2681314f
xilinx/axi_adxcvr/axi_adxcvr_up: Fix force error control bit
2021-03-22 10:17:10 +02:00
40baa63f0f
adrv2crr_fmcomms8: Fix system_top.v
2021-03-19 17:56:28 +02:00
93044adddf
axi_spi_engine: almost full and almost empty is generated by the util_axis_fifo
2021-03-18 18:53:35 +02:00
d91b50071f
axi_spi_engine: Fix IRQ generation
2021-03-18 18:53:35 +02:00
22ce3ef9ce
axi_spi_engine: Fix level/room width for the CDC FIFOs
2021-03-18 18:53:35 +02:00
c718ba91f1
axi_adrv9001: Add status bit for Tx clocking
...
If Tx source synchronous clock is not routed through clock capable pins
the interface and driving logic must run on the Rx interface clock.
This introduces a dependency, Rx interface must be bring up before the
Tx. In this mode a Tx only operation is not possible.
This is done through a synthesis parameter.
Expose this parameter to the software so it can query if the limitations
exists in the implementation.
2021-03-17 16:34:12 +02:00
c9ca1ac00a
util_axis_fifo: Improve GUI layout in Vivado
2021-03-12 15:06:45 +02:00
a1773c661c
adrv9009zu11eg_crr: Update spi
...
Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
3dce87d09b
ad9083: Add reference design for ad9083 eval board
2021-03-10 10:52:03 +02:00
dcec4fe1b7
adrv9001/zc706: Fix spaces
2021-03-10 10:35:52 +02:00
dc186645d8
adrv9001/zc706: Fix comments HPC to LPC
2021-03-10 10:35:52 +02:00
61c07ff9f1
util_axis_fifo: Add REMOVE_NULL_BEAT_EN feature
...
If the REMOVE_NULL_BEAT_EN is set, in FIFO mode, all the beats with a
NULL TKEEP will be removed from the AXI stream.
This feature is used initially in data_offload, to create a continues and
cyclic TX data stream for DACs, when the IPs in the path have different data
widths.
2021-03-08 11:32:40 +02:00
9611be9ded
util_axis_fifo: Add TKEEP support
2021-03-08 11:32:40 +02:00
0d3d099beb
util_axis_fifo: Fix FIFO is full alignment
2021-03-08 11:32:40 +02:00
8ce1d6bf36
util_axis_fifo: Switch data and tlast order, improve maintainability
2021-03-08 11:32:40 +02:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
...
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
e2a111d74b
jesd204/ad_ip_jesd204_tpl_dac: Drop LSBs from wider bus to be compatible with previous implementations
...
Add selectable synthesis option for dropping LSBs or MSBs
2021-03-08 10:46:52 +02:00
69bb9df515
jesd204_rx: Set ASYNC_REG attribute for double syncs
2021-03-08 10:46:52 +02:00
8d388dd4f2
jesd204_rx:jesd204_rx_ctrl_64b: Improve timing closure
2021-03-08 10:46:52 +02:00
c2f703f56b
jesd204/jesd204_rx: Make output pipeline stages opt in feature
2021-03-08 10:46:52 +02:00
fd714c181a
jesd204/ad_ip_jesd204_tpl_adc: Make frame alignment opt-in feature
2021-03-08 10:46:52 +02:00
0db7519c18
jesd204_tx:64b: Remove reset
...
Remove synchronous reset from datapath to reduce fanout on reset and
help timing closure.
2021-03-08 10:46:52 +02:00
2545e53b0b
jesd204_rx:64b: Remove reset
...
Remove synchronous reset from datapath to reduce fanout on reset and
help timing closure.
2021-03-08 10:46:52 +02:00
7b4fa390db
ad_ip_jesd204_tpl_dac: fix capability reg
2021-03-08 10:46:52 +02:00
1099badaf4
ad9082_fmca_ebz:zc706: Initial version
2021-03-05 15:54:23 +02:00
2213527f29
ad9082_fmca_ebz:zcu102: Initial version
2021-03-05 15:54:23 +02:00
f56e3c305b
ad9082_fmca_ebz:vcu118: Initial version
2021-03-05 15:54:23 +02:00
6b13b32f24
ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size
2021-03-04 11:13:29 +02:00
85729def2a
axi_adrv9001: Double sync control lines between interface 1 and 2
2021-03-04 11:13:10 +02:00
c691b5b0af
axi_ad9361: Update constraints in case TDD is disabled
2021-03-04 11:13:10 +02:00
677c154134
adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
...
Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
2021-03-04 11:13:10 +02:00
03de08609b
fmcomms2/zed: Disable unused TDD to save space and timing
2021-03-04 11:13:10 +02:00
50c4c3e815
axi_adrv9001: Fix channel 3 for Tx1 in DMA mode
2021-03-04 11:13:10 +02:00
3aa8a631d0
axi_adrv9001: Quartus 19.3 updates
2021-03-04 11:13:10 +02:00
0dd3173547
adrv9001/zc706: Initial commit
...
The project supports CMOS interface only.
VADJ on the ZC706 must be programmed to 1.8V
Instructions can be found here:
https://www.xilinx.com/Attachment/ZC706_Power_Controllers_Reprogramming_Steps.pdf
https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/ZC706-Doesn-t-work-with-VADJ-at-1-8v/td-p/430086
2021-03-03 09:03:03 +02:00
Laszlo Nagy
AndreiGrozav
stefan.raus
vladimirnesterov
Sergiu Arpadi
Istvan Csomortani