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8 Commits (6a6c5acc8ec422c068c7787cdeb5b0ee4ae1aa51)

Author SHA1 Message Date
Laszlo Nagy 97b92565b2 Makefile: Replace util_fifo2axi_bridge with util_hbm 2022-04-28 14:31:32 +03:00
Laszlo Nagy 8df1d8eade ad9081_fmca_ebz: Update parameter description 2022-03-11 13:16:22 +02:00
Laszlo Nagy e00def31d0 ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
Laszlo Nagy 731ed0a7a5 ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver 
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.

Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-19 14:01:48 +02:00
Laszlo Nagy 1d951cfbae ad9081_fmca_ebz/vck190: Change default profile to 2 lanes 2021-11-19 14:01:48 +02:00
Filip Gherman 9295218a64 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Laszlo Nagy 3a1babe366 ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock 
Reset transceiver with a pulse
 2021-10-05 14:09:51 +03:00
Laszlo Nagy 8d547f31e1 ad9081_fmca_ebz/vck190: Initial version 2021-10-05 14:09:51 +03:00