Commit Graph

13 Commits (6a6c5acc8ec422c068c7787cdeb5b0ee4ae1aa51)

Author SHA1 Message Date
Sergiu Arpadi 71009e74ff ad7768_if: Remove buffers, add parallel data path 2020-12-15 15:16:14 +02:00
sarpadi dd47e30431 ad7768_evb_sync: Fixed sync issue
fixed sync inside ad7768_if module;
2020-03-04 18:21:55 +02:00
Istvan Csomortani 554feaa1af util_pulse_gen: Update ports for all outdated instance
The new version of util_pulse_gen has different ports and port names.

Update all the instance:
  - AD738x_FMC
  - AD7768EVB
  - ADAQ7980_SDZ
2019-06-28 11:18:29 +03:00
Istvan Csomortani 7fa620d253 gtm_projects: Update system_top
In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.

Following projects were changed:

  - AD5766_SDZ
  - AD7134_FMC
  - AD7616_SDZ
  - AD77681EVB
  - AD7768EVB
  - ADAQ7980
2019-06-28 11:18:29 +03:00
Istvan Csomortani 21ce53f765 Revert "Move GTM projects to gtm_projects branch"
This reverts commit 171093eca4.
2019-06-28 11:18:29 +03:00
Adrian Costina 171093eca4 Move GTM projects to gtm_projects branch 2018-06-15 16:28:40 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Adrian Costina 98b58562d6 system_top: Non functional changes in system_tops to reduce warnings
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.

The following system_top modules were changed:
  - ad738x_fmc
  - ad7616_sdz
  - ad77681evb
  - ad77681evb
  - ad7768evb
  - ad9739a_fmc
  - ad9434
  - adrv9739
  - fmcadc5
  - ad6676evb
  - ad9265
  - ad5766
  - fmcomms5
  - m2k
2018-04-11 15:09:54 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty 0938041d97 ad7768evb: added 2015-12-07 13:07:03 -05:00