2856 Commits (6a6c5acc8ec422c068c7787cdeb5b0ee4ae1aa51)

Author	SHA1	Message	Date
Lars-Peter Clausen	6da9c65a08	axi_dmac: Add support for zero latency transfer switching ... Right now there is always a period of one clock cycle where we can not transfer any data when switching between two transfers. This patch modifies the data mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2014-03-07 18:39:20 +01:00
Rejeesh Kutty	23a62a92b2	up_adc_common: dma bus width is 0x8 (constant)	2014-03-06 19:22:19 -05:00
Adrian Costina	831c19ea84	Added axi_dmac, axi_fifo and misc files in library	2014-03-06 18:16:02 +02:00
Rejeesh Kutty	63bd2b870a	pointers to directories	2014-02-28 16:58:30 -05:00
Rejeesh Kutty	ff5021b1a8	pointers to directories	2014-02-28 16:57:19 -05:00
Rejeesh Kutty	f7c9368abc	initial checkin	2014-02-28 14:26:22 -05:00