up_xfer_done should signalize when a previous control set is
transferred to the other clock domain and the current control set is latched.
If a bit from the up_data_cntrl changes, it should stay in that state until
the up_xfer_done asserts.
When using a CLK_RATIO > 1 the first n samples(n=CLK_RATIO) after sync, are
noisy. This is because the phase accumulator data is passed to the phase to
amplitude converter, during the phase synchronization step.
This patch fixes an issue where the pulse width is only updated two
periods after the current one.
Signed-off-by: David Winter <david.winter@analog.com>
Add CMOS support for the interface for the following symbol modes on Xilinx devices:
A B C D E F G H
CSSI__1-lane 1 16/8 80(SDR)/160(DDR) 80 - SDR/DDR SDR/DDR->4/2(C=16), 2/1(C=8)
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate
CSSI - CMOS Source Synchronous Interface
Adds a magic identification value of 0x54444443 at word address 0x3.
It is derived from the ASCII String "TDDC" interpreted as a big-endian
32-bit unsigned integer.
Signed-off-by: David Winter <david.winter@analog.com>
If R1 mode is first syncronized to the dac clock domain will prevent its
usage if the dac clock is missing. In such case the synchronization will not
propagate.
Create a common 'run_tb.sh' script to be called by every testbench.
Unify file and testbenches names.
Fix util_pack/cpack_tb.
Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui)
Add ascript for that generates output in xml format (used by CI tools).
Build a large mux from smaller ones defined by the REQ_MUX_SZ parameter
Use EN_REG to add a register at the output of the small muxes to help
timing closure.
This commit adds two fields:
1. source channel selection - Sets the channel number the for the source data.
2. DMA enable mask - When this bit is set do not drive the enable line
towards the DMA interface.
Quartus Standard 19.1 throw a critical warning for registers that have
different reset and initial power-up level.
Do not initialize those registers so we can get rid of the warning.
Converting from RGB to YCbCr takes one less stage than converting
from YCbCr to RGB color space.
Moving extra delay stage(5), of the sync signals to a particular
YCbCr to RGB color space conversion case.
If dac_valid is not a constant '1' it gets synchronized with the
dac_data_sync signal. This causes that dac_valid never asserts while
dac_data_sync is high, this way skipping the phase initialization.
De-assert dac_rst together with an updated control set.
This allows writing the control registers before releasing the reset.
This is important at start-up when stable set of controls is required.
De-assert adc_rst together with an updated control set.
This allows writing the control registers before releasing the reset.
This is important at start-up when stable set of controls is required.
Allow monitoring of non-PN patterns which have zeros in it.
e.g. nible-ramp, full range ramp.
Singular zeros got ignored if not out of sync, while OOS_THRESHOLD
consecutive zeros or non-matching data asserts the out of sync line.
PopPaul2021
Laszlo Nagy
AndreiGrozav
David Winter
stefan.raus
Istvan Csomortani
alin724
Adrian Costina
sergiu arpadi