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6 Commits (6a6c5acc8ec422c068c7787cdeb5b0ee4ae1aa51)

Author SHA1 Message Date
David Winter 6be4ea92a7 library: axi_tdd: Make synchronization stage optional 
Signed-off-by: David Winter <david.winter@analog.com>
 2022-04-20 10:54:53 +03:00
David Winter 73468d662b axi_tdd: Add false paths to tdd sync input 
This allows the external synchronization input to be driven from
asynchronous sources like a 1 PPS signal or just signals from different
clock domains in general.

Signed-off-by: David Winter <david.winter@analog.com>
 2022-04-20 10:54:53 +03:00
LIacob106 076e81a17c library: Add link to wiki for IPs 2021-10-25 10:44:53 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
David Winter 30cc7d7420 axi_tdd: Add standalone axi_tdd IP core 
This commit adds a standalone TDD IP core based on the
existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge.

Signed-off-by: David Winter <david.winter@analog.com>
 2021-06-26 08:27:54 +03:00