Commit Graph

10 Commits (68959150769dce848dd36babfe00a07bc15aac36)

Author SHA1 Message Date
Istvan Csomortani ac2e5a9dac constraints: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
Istvan Csomortani 1156aeac16 ad_sysref_gen: Update SYSREF related constraints 2016-12-19 18:07:05 +02:00
Istvan Csomortani 67390c2a95 ad6676evb: Update projects with ad_sysref_gen 2016-12-19 10:52:25 +00:00
Istvan Csomortani 557efed5d9 ad6676evb: Update clock constraints 2016-12-14 17:55:49 +02:00
Istvan Csomortani d6918de19e ad6676: Update projects to xcvr frame work 2016-11-10 10:39:46 +02:00
Adrian Costina dca39c26f9 ad6676evb: Added clock constraint for the ADC path 2016-01-22 15:45:16 +02:00
Adrian Costina 33390c85f8 ad6676evb: Update ZC706 project 2015-09-25 14:46:02 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty 1da8356f05 ad6676evb: 2014.4 updates 2015-03-17 16:53:13 -04:00
Rejeesh Kutty 3211964c2e ad6676evb: added 2014-11-10 13:41:01 -05:00