6895915076
avl_dacfifo: Fix reset of write address register
...
Fix the reset of the dma_mem_waddr (write address register of the CDC
FIFO on DMA's clock domain). This solves the occasional invalid read backs after
multiple re-initialization of the PL_DDR_FIFO.
2017-11-01 12:21:56 +00:00
f692d7bc40
daq3: Disable start synchronization for the ADC DMA
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The ADC FIFO does not provide any sync output and for two channels it's not needed
2017-11-01 09:31:19 +02:00
2b4b9d7bab
daq2: Disable start synchronization for the ADC DMA
2017-10-31 17:16:08 +02:00
e3ea51ade3
avl_dacfifo: Refactor the fifo
...
+ Build both the read and write logic around an FSM
+ Consistent naming of registers and wires
+ Add support for burst lenghts higher than one, current burst lenght
is 64
+ Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
2017-10-31 14:30:06 +00:00
5b9e4cb692
daq2/zcu102: Pin Swap for ZCU102 Rev1.0
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2017-10-30 11:09:20 +00:00
22df03f9a4
daq3: A10GX, overconstrained failing paths
2017-10-28 08:21:50 +01:00
fe1adb6e4f
daq3: A10GX, updated to the ADI JESD204
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- changed lane rate to 12.33Gbps
- added dac fifo
2017-10-25 14:45:27 +01:00
1b1edd1b03
jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps
2017-10-25 14:36:54 +01:00
de5a21af80
daq2: A10GX, added additional interconnect pipelining
2017-10-23 16:39:58 +01:00
e8bab0b45f
adi_env: Normalize environment variables
...
If the ADI_HDL_DIR or ADI_PHDL_DIR are set on Windows platforms, an
invalid TCL character (e.g. backslash) may be used as a file separator,
causing issues with the build / library scripts.
Normalize the paths before using them as global TCL variables.
2017-10-23 12:15:14 +01:00
37323e3444
adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing
2017-10-20 13:46:22 +01:00
aa6af4e522
daq2: A10GX, added extra pipelining in the interconnect in order to improve timing
2017-10-20 13:45:05 +01:00
083962450a
daq2: A10GX, connect dac_fifo_bypass to gpio
2017-10-19 16:07:18 +03:00
e43056455c
daq2: A10SOC, added dac fifo
2017-10-12 14:16:05 +03:00
72d9c1c6f2
daq2: A10GX, added dac fifo
2017-10-11 12:52:15 +03:00
5a1e77b6dc
axi_ad9361: Fix dac_datarate counter implementation
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Update the dac_data_rate counter inmplementation to be infered as a
loadable down counter. This patch will prevent failing paths inside the counter.
2017-10-11 10:07:28 +01:00
06bab87733
axi_dmac: Reset fifo_rd_data when DMA is off - v2
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The first attempt (f3daf0) faild miserably. When the data_req signal
from the device had more than 1 cycle of deassert state, because of the
added latency of the data stream, the device got 'zeros' too.
In this fix, the DMA will hold the valid data on the bus, between two
consecutive data request. The bus is reseted just after all the data
were sent out.
2017-10-10 08:10:24 +01:00
d9acdb8092
usdrx1/a10gx: Add external flash support
2017-10-06 08:47:24 +01:00
baf8ec09a3
fmcjesdadc1/a10gx: Add external flash support
2017-10-06 08:46:22 +01:00
df70a6605c
daq3/a10gx: Add external falsh support
2017-10-06 08:45:33 +01:00
be4e02aed9
adrv9371x/a10gx: Add external flash support
2017-10-06 08:43:58 +01:00
bdd7e29bae
util_dacfifo: Integrate grey coder/decoder module
...
The grey coder/decoder function was limited to 10 bits, and this
resulted an unwanted limitation of the FIFO size. Using this
module, the coder/decoder data width can be adjusted to the current
address width.
2017-10-05 12:25:50 +01:00
f3daf0dacb
axi_dmac: Reset the fifo_rd_data if the DMA is off
...
Reset the fifo_rd_data if the DMA does not have an active transfer.
Becasue all the DAC device cores are transfering the data from the FIFO
interface to the data interface without any validation signal, DMA needs to put
the data bus into a known state, to prevent the device core to send the
last known data again and again.
2017-10-05 08:54:15 +01:00
d690a614c1
a10gx: Force all used tiles to high speed, in order to improve timing
2017-10-04 16:16:00 +01:00
03e744f0f1
daq1_zed: Lower the adc and daq clock to 450MHz
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The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
2017-10-04 13:01:14 +01:00
7a3c4ab81f
arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
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This fixes the bandwidth issue when data is streamed from the DDR and the system works at 61.44 MSPS
2017-10-04 13:01:14 +01:00
ee01ea3736
daq2/a10gx: Add cfi_flash to qsys
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+ Add cfi_flash to qsys
+ Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
a33f3178c2
adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled
2017-10-04 11:29:09 +01:00
a2ee478027
axi_ad9361: Fix incorrect merge
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Fix paramter propegation for DAC_CLK_EDGE_SEL
2017-10-03 10:51:35 +01:00
0064004d34
axi_dmac: Control s_axis_user/fifo_wr_sync validity
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The ports s_axis_user or fifo_wr_sync will be active just
if the SYNC_TRANSFER_START is enabled.
2017-10-03 09:32:14 +01:00
899b8436ad
arradio: Fix the last incorrect merge
2017-10-03 09:15:45 +01:00
08a31a7d9f
axi_dmac: Fix the last incorrect merge
2017-10-03 09:15:45 +01:00
49293f7a87
axi_ad9361: Fix the last incorrect merge
...
The last merge broke a couple of source files of this core. This
commit brings all the core to a functional state.
2017-10-03 09:15:23 +01:00
89bd8b44d4
Merge branch 'dev' into hdl_2017_r1
2017-09-26 07:42:19 +01:00
a386a42642
interface: Update the transceiver interfaces
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On commit 6d4430 the signal called sel was removed from the transceiver
interfaces. Update the interface definition script.
2017-09-25 18:02:04 +01:00
256dd87dd2
common/microzed: Enable PS CLK1 = 200MHz
2017-09-25 15:16:58 +03:00
07f3295638
common/a10soc: Update configuration for emif plddr4 IP
2017-09-25 08:57:26 +01:00
2926a6aaf9
altera/ad_mem_asym: Delete it, QSYS flow is used
2017-09-25 08:57:26 +01:00
700ed156ab
[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
2017-09-25 08:56:40 +01:00
3a47567f9c
common/a10gx: Chance SPI frequency from 128KHz to 10 MHz
2017-09-19 18:01:18 +03:00
55daa786fa
axi_adcfifo: Add missing constraints
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Add missing timing exceptions on paths between the DMA and DDR clock
domains. All these paths are properly synchronized using CDC in the HDL,
but are missing timing exceptions in the XDC file. This can lead to timing
errors when building a design using the axi_adc_fifo.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-13 19:52:48 +02:00
cafa811c74
adrv9379: Change the DMA clock to 250
2017-09-11 16:52:44 +03:00
58572d746c
arradio/c5soc- rd10102013_979 fix
2017-09-05 12:52:41 -04:00
c3aa3e8a9c
adrv9371: a10soc: Whitespace cleanup
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Remove some extra end-of-line whitespace.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-05 13:47:49 +02:00
6736aaeca1
arradio- add control/status ports
2017-09-01 14:39:18 -04:00
bb73e7a40f
arradio- add control/status ports
2017-09-01 14:39:18 -04:00
6ce4494002
adrv9379: Initial commit
2017-09-01 17:28:04 +03:00
9a32240cc5
axi_ad9379: Initial commit
2017-09-01 17:26:37 +03:00
cb2fd6af73
dm2k: Drive the ADC DMA valid from the trigger extracting core
2017-08-30 18:28:52 +03:00
6d5b5b50a5
axi_logic_analyzer: Compensate the 4 word latency of util_var_fifo
2017-08-30 18:17:41 +03:00
Istvan Csomortani
Adrian Costina
Michael Hennerich
Matt Fornero
AndreiGrozav
STEVE KRAVATSKY
Lars-Peter Clausen
Rejeesh Kutty