pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Adrian Costina	a753d506c5	axi_mc_controller: Removed channels, as no data needs to be streamed to DMA	2015-10-09 13:54:03 +03:00
Istvan Csomortani	57cfb7cfb1	hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N	2015-08-19 14:11:47 +03:00
Rejeesh Kutty	297e885981	library- drp moved to up-clock domain	2015-06-01 14:52:52 -04:00
Adrian Costina	5ac7ebb8a3	axi_mc_*: Removed delay pins from up_adc_common	2015-05-21 14:03:58 +03:00
Rejeesh Kutty	e918588a4b	library: remove axi-min-size parameter	2015-05-19 13:07:48 -04:00
Adrian Costina	6ee66df41e	axi_mc_controller: Updated for motor control revision 2	2015-04-01 11:41:33 +03:00
Adrian Costina	7e8e1e4fd0	axi_mc_controller: updated core to latest axi interface implementation	2014-12-05 11:52:59 +02:00
Lars-Peter Clausen	41cc92ef49	Remove BASEADDR/HIGHADDR parameters This is unused and unneeded. The AXI interconnect will make sure that a peripheral only gets requests that are meant for it, there is no need to check the address in the peripheral itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2014-09-11 12:26:37 +02:00
Lars-Peter Clausen	50faf0c53a	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
acozma	d08d0cd70b	motor_control: added the MW FOC IP and updated the design	2014-09-01 18:35:21 +03:00
Adrian Costina	54b2cd74bf	motor_control: cores modified so they can compile with the new common files	2014-07-23 11:58:50 +03:00
Adrian Costina	01de117b5f	motor_control: Changed controller to PID controller. Some estetic changes	2014-04-28 17:57:51 +03:00

12 Commits (66d4f8fd5800175b962afb79a17a8f2b148fdced)