Commit Graph

10 Commits (6621fbec61b302acb5c02f9d87411418d509d84a)

Author SHA1 Message Date
Laszlo Nagy 08d01789c8 microblaze: add SPI clock constraint
The SPI clock is a generated clock from the system clock. Worst case
scenario is that the system clock is divided by two.
2019-05-30 14:55:11 +03:00
Laszlo Nagy fe2b43ddd9 base:constraint: Setting Configuration Bank Voltage Select
Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

The following base constraints were updated:
 - kcu105
 - kc705
 - vc707
 - ac701
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty 1fcccacdf5 kc705/vc707: consistency fixes 2015-03-26 14:00:50 -04:00
Rejeesh Kutty daac204676 kc705: gpio bd 2015-03-26 10:14:12 -04:00
Istvan Csomortani cea2d90eb2 base_kc705: Fix different issues
+ No more constant block inside IPI.
+ Gpio switch/led is on the axi_gpio first channel.
+ Fix the address map
+ Remove hdmi/spdif related constraints from base constraints
2015-03-16 19:10:57 +02:00
Istvan Csomortani 5baa015246 kc705_base: Delete timing constraints 2014-11-13 16:30:37 +02:00
Adrian Costina 05ed98f884 common: Updated common constratins for ac701, kc705, vc707, zc702 2014-11-11 12:35:44 +02:00
Rejeesh Kutty 5c3b65d01b adv7511: kc705/ac701 updates 2014-03-06 09:36:50 -05:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00