4 Commits (660dddf1e81ee8bcf3ac9c0c13e36b9212103fa7)

Author	SHA1	Message	Date
Adrian Costina	eda585f0e4	m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2	2017-02-27 14:16:32 +02:00
Adrian Costina	908da60ab6	m2k: zed, changed constraints so they are the same with the ZED default configuration ... - the voltage can be physically changed between 1.8V, 2.5V and 3.3V	2017-02-27 14:13:34 +02:00
Rejeesh Kutty	c598e84258	remove processing order (no clock def dependency)	2017-02-22 16:02:08 -05:00
Adrian Costina	b14d740f87	M2K: initial commit	2017-01-31 16:43:40 +02:00