Rejeesh Kutty
|
cb3d1883bc
|
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
|
2017-02-17 15:21:33 -05:00 |
|
Rejeesh Kutty
|
18660c7ab4
|
fmcjesdadc1/a5gt: ddr3 use ip constraints
|
2016-12-22 14:14:21 -05:00 |
|
Rejeesh Kutty
|
1ceec2e2a9
|
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
|
2016-12-22 14:14:21 -05:00 |
|
Rejeesh Kutty
|
959055bd54
|
common/a5gt- updates
|
2016-11-10 16:56:35 -05:00 |
|
Rejeesh Kutty
|
c6730ab2d7
|
fmcjesdadc1/a5gt- updates
|
2016-11-10 11:36:41 -05:00 |
Adrian Costina
|
31ab81d627
|
a5gt: Updated ethernet clock constraints
|
2015-07-27 16:02:51 +03:00 |
|
Rejeesh Kutty
|
a1733238df
|
fmcjesdadc1- base/board split up
|
2015-07-23 15:21:53 -04:00 |
|
Rejeesh Kutty
|
15740a7d34
|
fmcjesdadc1- 15.0 updates
|
2015-06-24 05:31:09 -04:00 |
|
Rejeesh Kutty
|
a8a71b4971
|
alt-tq: common file
|
2015-06-04 11:00:25 -04:00 |
|
Adrian Costina
|
5a77ab0161
|
a5gt:common: Added phy reset signal from ethernet in pin assignments
|
2015-01-23 12:31:41 +02:00 |
|
Rejeesh Kutty
|
3deb55bb98
|
a5gt: ethernet i/o changed to lvds
|
2014-09-04 11:19:24 -04:00 |
|
Rejeesh Kutty
|
cb29b83b05
|
a5gt: updates to match a5gt
|
2014-08-25 10:46:59 -04:00 |
|
Rejeesh Kutty
|
04ab34c8ed
|
a5gt: ethernet assignments
|
2014-04-03 20:50:16 -04:00 |
|
Rejeesh Kutty
|
0d678b89ed
|
altera a5gt fmcjesdadc1 setup
|
2014-04-01 11:46:37 -04:00 |