3 Commits (660dddf1e81ee8bcf3ac9c0c13e36b9212103fa7)

Author	SHA1	Message	Date
Adrian Costina	37a1c98c12	axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching	2017-02-27 14:19:54 +02:00
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Adrian Costina	6604cc7322	axi_logic_analyzer: Initial commit	2017-01-31 16:23:56 +02:00