660dddf1e8
util_dacfifo: Define constraints for bypass
2017-03-07 16:14:46 +02:00
7559d23873
util_dacfifo/constraints- false paths for bypass
2017-03-06 10:33:07 -05:00
7478777d8d
axi_dacfifo: Match the ports with util_dacfifo
2017-03-03 18:46:16 +02:00
760228d676
util_dacfifo: Update the util_dacfifo
...
Fix bypass and undate the general functionality. If bypass enabled
the FIFO will function as a normal CDC FIFO.
2017-03-03 18:43:36 +02:00
e0d4607692
adcfifo- asym_mem primitive changes
2017-03-01 15:55:56 -05:00
3586397f57
altera/common- add asymmetric fifo
2017-03-01 15:35:04 -05:00
9c65166e26
ad9371- missing net declarations
2017-02-28 13:31:23 -05:00
104e9dfcdc
adc/dac-fifo altera cores
2017-02-28 13:30:50 -05:00
0d231935ef
library/util_dacfifo- match bypass port with axi_dacfifo
2017-02-27 16:06:39 -05:00
1d6ddacfd6
axi_ip_constr: Fix constraints
...
The filter for CDC registers were too generic, and a few non-CDC
register were set as asynchronous register.
2017-02-27 16:25:09 +02:00
1c8e63cb68
axi_adc_trigger: Added triggered register
2017-02-27 14:26:19 +02:00
37a1c98c12
axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching
2017-02-27 14:19:54 +02:00
11623e79be
axi_dacfifo: Fix clock for read address generation
2017-02-24 15:47:04 +02:00
3e596347fd
axi_dacfifo: Delete unused wires
2017-02-24 15:45:51 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
f326c03ff3
axi_dacfifo: Define constraint for bypass
...
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-02-24 12:35:42 +02:00
b9d3039568
axi_dacfifo: Register the dac_valid signals
2017-02-24 12:34:58 +02:00
debc6e2066
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-02-24 12:32:25 +02:00
dfcd5214a0
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
2017-02-24 12:28:46 +02:00
6b90054343
axi_ad9361: Define CDC constraint for tdd_sync
2017-02-24 11:24:07 +02:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
573959c826
Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy
2017-02-23 16:16:34 +02:00
d820d3d245
util_sync_constr: Preserve 1bit CDCs with ASYNC_REG true
2017-02-23 11:44:01 +02:00
94bda1d415
axi_ad9361: Preserve 1bit CDCs with ASYNC_REG true
2017-02-23 11:43:10 +02:00
2da7dd4079
axi_ip_constr: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-23 11:33:25 +02:00
2b354af876
axi_ad9361_tdd: Register the tdd_sync_cntr output
2017-02-23 11:31:23 +02:00
e3ac341aad
axi_dacfifo: Fix constraints
2017-02-21 14:45:18 +02:00
981a61bf16
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
2017-02-17 18:40:02 +02:00
f10866e4c3
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
2017-02-16 19:54:41 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
358aa48c76
axi_adc_decimate: Fix assignment width
2017-02-15 11:38:43 +02:00
c6ee76421b
axi_usb_fx3: Fixed clock domain association
2017-02-14 11:48:07 +02:00
7c86b038ef
util_fir_int: manually request data at 1/8 clock frequency
2017-02-13 18:05:59 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
0dae754f2d
axi_adxcvr: Add rparam register to Altera XCVR
2017-02-10 16:19:17 +02:00
24daffcf5c
spi_engine: Set up default driver value for input ports
2017-02-07 12:30:46 +02:00
47db0d80fe
axi_ad7616: Set up default driver value for input ports
2017-02-07 12:29:21 +02:00
a57fb5f82f
library/ad9122- constraints clean-up
2017-02-02 14:21:41 -05:00
1e54b5230f
axi_adxcvr- add m_axi associated clock
2017-02-02 11:17:56 -05:00
806d19febc
axi_adxcvr- add primitive info read
2017-02-01 13:38:29 -05:00
1c9d8c4e7c
axi_adxcvr- add primitive info read
2017-02-01 13:35:02 -05:00
1df6178ab8
library: Update common Makefile
2017-01-31 16:44:32 +02:00
7387df9d13
util_var_fifo: Initial commit
2017-01-31 16:26:45 +02:00
b9c94f63a5
util_extract: Initial commit
2017-01-31 16:26:05 +02:00
6604cc7322
axi_logic_analyzer: Initial commit
2017-01-31 16:23:56 +02:00
9c975211da
axi_dac_interpolate: Initial commit
2017-01-31 16:22:49 +02:00
4a7232cbcb
axi_adc_decimate: Initial commit
2017-01-31 16:21:39 +02:00
35b97abc6d
axi_adc_trigger: Initial commit
2017-01-31 16:20:13 +02:00
fb945ac51c
axi_ad9963: Initial commit
2017-01-31 16:18:58 +02:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
Istvan Csomortani
Rejeesh Kutty
Adrian Costina