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314 Commits (659e0cca4e31c4e379a80408f4480447010b5bcc)

Author SHA1 Message Date
Istvan Csomortani 659e0cca4e cftl_cip: Initial check in. 
Project cftl_cip supports the following Circuits from the Lab pmods:
 + EVAL-CN0350-PMDZ
 + EVAL-CN0335-PMDZ
 + EVAL-CN0336-PMDZ
 + EVAL-CN0337-PMDZ
Note: Additional testing needed!
 2015-01-23 18:29:32 +02:00
Rejeesh Kutty 5a1819ed6e fifo2s: qualify last with valid 2015-01-15 15:42:10 -05:00
Rejeesh Kutty debbe31713 Merge remote-tracking branch 'origin/master' into dev 2015-01-09 11:12:56 -05:00
Rejeesh Kutty 63633a0fa5 ad9739a: constraints 2015-01-08 10:25:45 -05:00
Rejeesh Kutty ed73a9d1cf ad9739a: updated to ad9739a 2015-01-08 10:25:15 -05:00
Istvan Csomortani 14df46c193 library: Initial commit of axi_hdmi_rx ip core 
Status unknown, NOT tested.
 2015-01-08 16:58:56 +02:00
Istvan Csomortani 9f485f2f4e common: Add register map module for HDMI receiver. 2015-01-08 12:24:47 +02:00
Istvan Csomortani 161e6cc70d common: Add color space sampling and color space conversion modules 
This two module are used by the HDMI receiver.
 2015-01-08 12:24:46 +02:00
Rejeesh Kutty ad4b4f64d0 ad9739a: ad9122 copy 2015-01-07 15:36:02 -05:00
Rejeesh Kutty 3a4d765a2b up_clkgen: reading typo 2015-01-07 14:02:39 -05:00
Rejeesh Kutty b65bcab8d6 up_clkgen: reading typo 2015-01-07 13:58:43 -05:00
Rejeesh Kutty 5f93c859b5 util_rfifo: renamed ports to make vivado happy 2015-01-06 16:16:42 -05:00
Rejeesh Kutty 8056574bae util_wfifo: renamed ports to make vivado happy 2015-01-06 16:16:25 -05:00
Rejeesh Kutty 0291bb3bf7 util_rfifo: port name fixes & doc. 2015-01-06 16:15:51 -05:00
Rejeesh Kutty 36b041ccc0 util_wfifo: port name fixes & doc. 2015-01-06 16:15:42 -05:00
Rejeesh Kutty ee0912eb6a ad9361: make 2t2r external for mw 2015-01-05 10:54:23 -05:00
Rejeesh Kutty c3529f112f up_gt: move status to up clock 2014-12-19 13:00:27 +02:00
Rejeesh Kutty f4774d6f98 fifo2s: false path typo on source signals 2014-12-19 13:00:13 +02:00
Rejeesh Kutty 1d6ea64d04 up_gt: move status to up clock 2014-12-16 08:48:13 -05:00
Rejeesh Kutty 16f64a75d6 fifo2s: false path typo on source signals 2014-12-15 13:00:13 -05:00
Rejeesh Kutty 04c10abc2f gth/gtx: share same cpll/qpll cpu settings 2014-12-11 11:18:48 -05:00
Istvan Csomortani c4152627f0 plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width 
The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long,
it needs to be just one adc_clk cycle.
 2014-12-09 13:59:19 +02:00
Istvan Csomortani 19732d89fb plddr3: Fix the adc_dwr pulse width 
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
 2014-12-09 13:51:00 +02:00
Adrian Costina 6aad2fbbb2 axi_hdmi_tx: Fixed typo in altera related core 2014-12-09 10:19:03 +02:00
Adrian Costina 6f8c259961 axi_hdmi_tx: Fixed typo in altera related core 2014-12-09 09:56:14 +02:00
Adrian Costina a70d27c094 axi_mc_speed: updated core to latest axi interface implementation 2014-12-05 11:53:11 +02:00
Adrian Costina 26f58914e2 axi_mc_current_monitor: updated core to latest axi interface implementation 2014-12-05 11:53:06 +02:00
Adrian Costina 7e8e1e4fd0 axi_mc_controller: updated core to latest axi interface implementation 2014-12-05 11:52:59 +02:00
Adrian Costina ea1a50c985 axi_mc_speed: updated core to latest axi interface implementation 2014-12-05 11:46:20 +02:00
Adrian Costina 0d2888a5a6 axi_mc_current_monitor: updated core to latest axi interface implementation 2014-12-05 11:45:37 +02:00
Adrian Costina 21591dc485 axi_mc_controller: updated core to latest axi interface implementation 2014-12-05 11:43:59 +02:00
Lars-Peter Clausen 6197563506 up_axi: Fix up_raddr/up_waddr port width 
Make sure that the port declaration width matches with the reg declaration
later on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-12-01 13:45:45 +01:00
Lars-Peter Clausen 8cc9adfc49 up_axi: Fix up_raddr/up_waddr port width 
Make sure that the port declaration width matches with the reg declaration
later on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-12-01 13:22:28 +01:00
Rejeesh Kutty afddc45ba4 library/ccat: initial commit 2014-11-25 12:59:51 -05:00
Rejeesh Kutty 196e8b119c library/bsplit: initial commit 2014-11-25 12:59:50 -05:00
Rejeesh Kutty 403f8c0631 util_cpack: ipi doesn't like local params 2014-11-21 15:32:13 -05:00
Rejeesh Kutty 3b500bafcc util_cpack: add port controls on ipi 2014-11-21 15:32:12 -05:00
Rejeesh Kutty 5ca2944b70 library/util_cpack: initial checkin 2014-11-21 15:32:10 -05:00
Istvan Csomortani 42874bfe81 prcfg_library: Major update 
Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
 2014-11-18 10:05:52 +02:00
Rejeesh Kutty a4724f8396 es: added kcu105 gth 2014-11-17 09:55:12 -05:00
Rejeesh Kutty b1c91fac92 es: added kcu105 gth 2014-11-17 09:55:10 -05:00
Rejeesh Kutty fd305f2eff es: added kcu105 gth 2014-11-17 09:55:09 -05:00
Adrian Costina 6dd1226696 axi_ad9643: Fixed constraint file 2014-11-17 12:12:09 +02:00
Adrian Costina 8831d9dbd7 axi_ad9122: fixed constraint file 2014-11-17 12:11:20 +02:00
Adrian Costina 2744d0cb37 util_wfifo: Update to implement flip flops 2014-11-17 12:10:21 +02:00
Rejeesh Kutty 41ffc66c26 fifo2s: removed m interface 2014-11-13 15:00:03 -05:00
Rejeesh Kutty 8761db438e axi_fifo2f: common interface with fifo2s 2014-11-12 15:15:32 -05:00
Rejeesh Kutty 925e966eb6 axi_fifo2s: fifo full replaced with ready 2014-11-12 14:43:47 -05:00
Rejeesh Kutty 5fc4f1b000 axi_fifo2s: buswidth fix 2014-11-12 14:43:46 -05:00
Rejeesh Kutty d204a7c2b7 axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:44 -05:00