Commit Graph

84 Commits (6565c5d018d1eef7b5803e0864463b726d043852)

Author SHA1 Message Date
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Istvan Csomortani 86b611c1f7 data_offload: Initial commit 2021-08-06 11:55:24 +03:00
Istvan Csomortani 157a8dee17 util_fifo2axi_bridge: Initial commit 2021-08-03 23:02:17 +03:00
David Winter 30cc7d7420 axi_tdd: Add standalone axi_tdd IP core
This commit adds a standalone TDD IP core based on the
existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge.

Signed-off-by: David Winter <david.winter@analog.com>
2021-06-26 08:27:54 +03:00
Laszlo Nagy 64f6762a05 library:axi_adrv9001: Initial version
ADRV9001 interfacing IP supports the following modes on Xilinx devices:

A              B  C       D       E       F      G        H
CSSI__1-lane   1  32      80      80      2.5    SDR      8
CSSI__1-lane   1  32      160     80      5      DDR      4
CSSI__4-lane   4  8       80      80      10     SDR      2
CSSI__4-lane   4  8       160     80      20     DDR      1
LSSI__1-lane   1  32      983.04  491.52  30.72  DDR      4
LSSI__2-lane   2  16      983.04  491.52  61.44  DDR      2

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
LSSI - LVDS Source Synchronous Interface

Intel devices supports only CSSI modes.
2020-08-24 17:49:12 +03:00
Istvan Csomortani 75d1379618 axi_laser_driver: Initial commit
The laser driver contains the axi_pulse_gen's IP and an additional
register map which controls/monitor the laser driver enable control line
and the over temperature warning line (OTW).

It also contains an interrupt logic, which allows to generate an
interrupt in function of the generated pulse or incoming OTW signal.

The IPs register maps looks as follow:

0x00 - axi_pulse_gen register map
0x80 - axi_laser_driver register map
  0x80 - DRIVER_ENABLE
  0x84 - DRIVER_OTW
  0x88 - EXT_CLK_COUNTER
  0xA0 - IRQ_MASK
  0xA4 - IRQ_SOURCE
  0xA8 - IRQ_PENDING
  0xAC - SEQUENCER_CONTROL
         0 - SEQUENCER_ENABLE
         1 - AUTO_SEQUENCER_ENABLED
  0xB0 - SEQUENCER_SYNC_OFFSET
  0xB4 - AUTO_SEQUENCE
         [ 1: 0] - CHANNEL_SEL_0
         [ 5: 4] - CHANNEL_SEL_1
         [ 9: 8] - CHANNEL_SEL_2
         [13:12] - CHANNEL_SEL_3
  0xB8 - MANUAL_SEQUENCE
         [ 1: 0] - MANUAL_CHANNEL_SEL

Current interrupt sources scheme is:
    - bit 0 : pulse (triggered by the level of the pulse)
    - bit 1 : OTW_N enter (triggered by positive edge of the OTW_N)
    - bit 2 : OTW_N exit (triggered by the level of the pulse)

Generate a reset signal before the pulse which can be used to reset
various IP's of the data path (eg. pack/cpack). This can help to clear out the
internal buffers and registers of these IP, starting clean at the moment when
the actual pulse arrives.

The sequencer has an auto and a manual mode, and can be set to custom
sequences of the TIA channel selection lines sate.

The sequencer in auto mode is synchronized to the pulse, it will change
its state before a generated pulse which will drive the lasers. The
offset between the sequencer beat and the laser driver pulse can be
modified through an AXI register.
2019-08-08 14:26:07 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani 2f0dbe6151 intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym 2019-06-29 06:53:51 +03:00
Istvan Csomortani 1e074726db intel_serde: Rename alt_serdes to intel_serdes 2019-06-29 06:53:51 +03:00
Istvan Csomortani b0fbe1bb57 util_clkdiv: Seperate the IP source into an intel and xilinx version 2019-06-29 06:53:51 +03:00
Istvan Csomortani 84bd50d437 alt_ifconv: Remove unused IP 2019-06-29 06:53:51 +03:00
Istvan Csomortani d5e5fcf17a alt_mul: Remove unused IP 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Istvan Csomortani 6668accc96 ad7405 : Initial commit
This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
2019-06-28 11:18:29 +03:00
Istvan Csomortani ba36c9cd57 makefile: Add axi_fan_control to library 2019-05-29 10:23:24 +03:00
Istvan Csomortani 0e7b38ebcf axi_pulse_gen: Initial commit
The axi_pulse_gen is a generic PWM generator, which can be configured
through an AXI Memory Mapped interface.

The current register map look like follows:

  0x00 - VERSION
  0x04 - ID
  0x08 - SCRATCH
  0x0C - IDENTIFICATION - 0x504c5347 which stands for 'PLSG' in ASCII
  0x10 - CONFIGURATION - contains reset and load bits
  0x14 - PULSE_PERIOD
  0x18 - PULSE_WIDTH

Also update all the other modules, which instantiate the util_pulse_gen.
2019-03-20 08:21:22 +00:00
Lars-Peter Clausen a0309e3e3a Remove old util_cpack and util_upack core
All projects have been updated to use the new pack/unpack infrastructure.
The old util_cpack and util_upack cores are now unused an can be removed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 0a30cdbf99 Add util_cpack2 core
The util_cpack2 core is similar to the util_upack core. It packs, or
interleaves, a data from multiple ports into a single data. Ports can
optionally be enabled or disabled.

On the input side the cpack2 core uses a multi-port FIFO interface. There
is a single data write signal (fifo_wr_en) for all ports. But each port can
be individually enabled or disabled using the enable signals.

On the output side the cpack2 core uses a single port FIFO interface. When
data is available on the output interface the data write signal
(packed_fifo_wr_en). Data on the packed_fifo_wr_data signal is only valid
when packed_fifo_wr_en is asserted. At other times the content is
undefined. The cpack2 core offers no back-pressure. If data is not consumed
when it is made available it will be lost.

Data from the input ports is accumulated inside the cpack2 core and if
enough data is available to produce a full output vector the data is
forwarded.

This core is build using the common pack infrastructure. The core that is
specific to the cpack2 core is mainly only responsible for generating the
control signals for the external interfaces.

The core is accompanied by a test bench that verifies correct behavior for
all possible combinations of enable masks.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 90540bf447 Add util_upack2 core
The util_upack2 core is similar to the util_upack core. It unpacks, or
deinterleaves, a data stream onto multiple ports.

The upack2 core uses a streaming AXI interface for its data source instead
of a FIFO interface like the upack core uses.

On the output side the upack2 core uses a multi-port FIFO interface. There
is a single data request signal (fifo_rd_en) for all ports. But each port
can be individually enabled or disabled using the enable signals.

This modified architecture allows the upack2 core to better generate the
valid and underflow control signals to indicate whether data is available
in a response to a data request.

If fifo_rd_en is asserted and data is available the fifo_rd_valid signal
are asserted in the following clock cycle. The enabled fifo_rd_data ports
will be contain valid data during the same clock cycle as fifo_rd_valid is
asserted. During other clock cycles the output data is undefined. On
disabled ports the data is always undefined.

If no data is available instead the fifo_rd_underflow signal is asserted in
the following clock cycle and the output of all fifo_rd_data ports is
undefined.

This core is build using the common pack infrastructure. The core that is
specific to the upack2 core is mainly only responsible for generating the
control signals for the external interfaces.

The core is accompanied by a test bench that verifies correct behavior for
all possible combinations of enable masks.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
AndreiGrozav b6663c6e0d jesd204: Update Makefiles
Fix jesd204 library build.
2018-06-11 11:30:47 +03:00
Lars-Peter Clausen e4c9c8734c library: Add a generic JESD204 DAC receiver core
For most of the DACs that use JESD204 as the data transport the digital
interface is very similar. They are mainly differentiated by number of
JESD204 lanes, number of converter channels and number of bits per sample.

Currently for each supported converter there exists a converter specific
core which has the converter specific requirements hard-coded.

Introduce a new generic core that has the number of lanes, number of
channels and bits per sample as synthesis-time configurable parameters. It
can be used as a drop-in replacement for the existing converter specific
cores.

This has the advantage of a shared and reduced code base. Code improvements
will automatically be available for all converters and don't have to be
manually ported to each core individually.

It also makes it very easy to introduce support for new converters that
follow the existing schema.

Since the JESD204 framer is now procedurally generated it is also very
easy to support board or application specific requirements where the lane
to converter ratio differs from the default (E.g. use 2 lanes/2 converters
instead of 4 lanes/2 converters).

This new core is primarily based on the existing axi_ad9144.

For the time being the core is not user instantiatable and will only be
used as a based to re-implement the converter specific cores. It will be
extended in the future to allow user instantiation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 17:21:20 +02:00
Lars-Peter Clausen 3516c4ca83 library: Add a generic JESD204 ADC receiver core
For most of the ADCs that use JESD204 as the data transport the digitial
interface is very similar. They are mainly differentiated by number of
JESD204 lanes, number of converter channels and number of bits per sample.

Currently for each supported converter there exists a converter specific
core which has the converter specific requirements hard-coded.

Introduce a new generic core that has the number of lanes, number of
channels and bits per sample as synthesis-time configurable parameters. It
can be used as a drop-in replacement for the existing converter specific
cores.

This has the advantage of a shared and reduced code base. Code improvements
will automatically be available for all converters and don't have to be
manually ported to each core individually.

It also makes it very easy to introduce support for new converters that
follow the existing schema.

Since the JESD204 deframer is now procedurally generated it is also very
easy to support board or application specific requirements where the lane
to converter ratio differs from the default (E.g. use 2 lanes/2 converters
instead of 4 lanes/2 converters).

This new core is primarily based on the existing axi_ad9680.

For the time being the core is not user instantiatable and will only be
used as a based to re-implement the converter specific cores. It will be
extended in the future to allow user instantiation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 17:21:20 +02:00
Adrian Costina e4d579726d Renamed ad9379 to adrv9009 2018-04-26 18:19:11 +03:00
Lars-Peter Clausen 1ea3ad28ae Add quiet mode to the Makefile system
The standard Makefile output is very noisy and it can be difficult to
filter the interesting information from this noise.

In quiet mode the standard Makefile output will be suppressed and instead a
short human readable description of the current task is shown.

E.g.
	> make adv7511.zed
	Building axi_clkgen library [library/axi_clkgen/axi_clkgen_ip.log] ... OK
	Building axi_hdmi_tx library [library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK
	Building axi_i2s_adi library [library/axi_i2s_adi/axi_i2s_adi_ip.log] ... OK
	Building axi_spdif_tx library [library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK
	Building util_i2c_mixer library [library/util_i2c_mixer/util_i2c_mixer_ip.log] ... OK
	Building adv7511_zed project [projects/adv7511/zed/adv7511_zed_vivado.log] ... OK

Quiet mode is enabled by default since it generates a more human readable
output. It can be disabled by passing VERBOSE=1 to make or setting the
VERBOSE environment variable to 1 before calling make.

E.g.
	> make adv7511.zed VERBOSE=1
	make[1]: Entering directory 'library/axi_clkgen'
	rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui
	*.ip_user_files *.srcs *.hw *.sim .Xil .timestamp_altera
	vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1
	...

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 2b914d33c1 Move Altera IP core dependency tracking to library Makefiles
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.

For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.

Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.

Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.

This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani cd94f2f249 util_axis_upscale: Initial commit
This module upscale an n*sample_width data bus into a 16 or 32*n data
bus. The samples are right aligned and supports offset binary or two's
complement data format.
2018-04-11 15:09:54 +03:00
Istvan Csomortani 377848ef52 cftl: Delete unused projects and libraries 2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Adrian Costina b54dab33e0 Make: Update makefiles 2017-11-20 14:27:39 +02:00
Istvan Csomortani 6ebef5dde0 make: Update make files 2017-06-26 15:51:19 +01:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 6ea87d094e util_delay: Initial commit
Generic module to introduce a fix N cycle delay into a datapath.
2017-05-25 15:12:10 +03:00
Lars-Peter Clausen 1202286c3d Add ADI JESD204 link layer cores
The ADI JESD204 link layer cores are a implementation of the JESD204 link
layer. They are responsible for handling the control signals (like SYNC and
SYSREF) and controlling the link state machine as well as performing
per-lane (de-)scrambling and character replacement.

Architecturally the cores are separated into two components.

1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take
care of the JESD204 protocol handling. They have configuration and status
ports that allows to configure their behaviour and monitor the current
state. The processing cores run entirely in the lane_rate/40 clock domain.

They have a upstream and a downstream port that accept and generate raw PHY
level data and transport level payload data (which is which depends on the
direction of the core).

2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The
configuration interface cores provide a register map interface that allow
access to the to the configuration and status interfaces of the processing
cores. The configuration cores are responsible for implementing the clock
domain crossing between the lane_rate/40 and register map clock domain.

These new cores are compatible to all ADI converter products using the
JESD204 interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 858065d49b library: Sort Makefile
Sort the entries in the library Makefile alphabetical. Keeping it ordered
makes it easier to track changes compared to randomly reshuffling it
every time a new entry is added.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
Rejeesh Kutty 391a14be7a hdlmake.pl updates 2017-05-04 13:59:47 -04:00
Istvan Csomortani 6387b53266 ad77681evb: Initial commit 2017-05-04 12:19:11 +03:00
Rejeesh Kutty 956753ca9c hdlmake- updates 2017-04-27 15:11:01 -04:00
Istvan Csomortani a2c20551a2 axi_ad5766: Add Makefiles for the core 2017-04-27 11:22:31 +03:00
Adrian Costina 7cff12107e hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile 2017-04-26 09:58:17 +03:00
Rejeesh Kutty cfd4e006b3 hdlmake updates 2017-04-25 15:46:26 -04:00
Lars-Peter Clausen 450c5ac74a Add CIC filter helper module
Add a helper module that provides the building blocks of a CIC filter.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 71469490c6 Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface
The read and write interfaces of a AXI bus are independent other than that
they use the same clock. Yet when connecting a single read-only and a
single write-only interface to a Xilinx AXI interconnect it instantiates
arbitration logic between the two interfaces. This is dead logic and
unnecessarily utilizes the FPGAs resources.

Introduce a new helper module that takes a read-only and a write-only AXI
interface and combines them into a single read-write interface. The only
restriction here is that all three interfaces need to use the same clock.

This module is useful for systems which feature a read DMA and a write DMA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Istvan Csomortani 5fa6dba333 Make: Update Makefiles 2017-02-10 16:32:58 +02:00
Adrian Costina 1df6178ab8 library: Update common Makefile 2017-01-31 16:44:32 +02:00
Istvan Csomortani 57bd6acd0f library: Update make file 2017-01-19 15:27:31 +02:00
Istvan Csomortani 1f7d19688a Update Makefile 2017-01-12 15:58:32 +02:00