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10 Commits (647a26e19ced81fb044f438a46d06c32d5da359f)

Author SHA1 Message Date
Lars-Peter Clausen 0da7b6eaa1 axi_dmac: axi_dmac_alt.v: Set default transfer length width to 24 
This is the same as the default value in axi_dmac.v

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-09 15:07:35 +02:00
Lars-Peter Clausen a4b9b1254a axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling 
We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.

Also set rlast to 1 instead of 0.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-09 15:05:06 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Rejeesh Kutty 280260e54c c5soc: dmac separated slave and master id widths 2014-08-22 09:08:54 -04:00
Rejeesh Kutty a5e3a07375 dma: altera fix id assignments 2014-08-11 16:46:36 -04:00
Rejeesh Kutty 314ec3d343 altera-9250/dma: make id width generic 2014-04-24 14:54:19 -04:00
Lars-Peter Clausen dc7b3e085c axi_dmac: Fix issues with non 64-bit AXI masters 
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 14:54:22 +02:00
Rejeesh Kutty 724bd70a06 altera additions and replacements 2014-04-01 11:18:10 -04:00
Rejeesh Kutty d3d26e1220 lower the address space requirements 2014-03-26 11:03:45 -04:00
Rejeesh Kutty ef960a29c7 altera files 2014-03-24 13:27:27 -04:00