pluto_hdl_adi

Author	SHA1	Message	Date
Lars-Peter Clausen	09ffe42603	ad_lvds_in: Allow to disable IDELAY The IDELAY is not always required, but it eats up power when instantiated. Allow to disable it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2017-04-18 12:17:39 +02:00
Lars-Peter Clausen	45f87b46c2	ad_lvds_in: Use "SAME_EDGE" mode Currently the IDDRs are configured in SAME_EDGE_PIPELINED mode, but then the negative data is delayed by an additional clock cycle. This is the same behaviour as using the IDDR in SAME_EDGE mode. Switching to SAME_EDGE mode removes extra pipelining registers while maintaining the same behaviour. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2017-04-18 12:17:39 +02:00
Rejeesh Kutty	a2b2ebbed2	ad_lvds_in- ultrascale/ultrascale+ sim device mess	2017-01-21 20:54:21 -05:00
Rejeesh Kutty	cc6ca4f0f2	ad_lvds_in- ultrascale sim device	2016-10-10 10:39:47 -04:00
Rejeesh Kutty	6b956066ef	xilinx/ad_lvds*- ultrascale+	2016-09-30 11:55:10 -04:00
Istvan Csomortani	b806fa3b42	lib_refactoring: Move all the Xilinx common modules to library/xilinx/common	2016-08-08 15:06:10 +03:00