Commit Graph

67 Commits (63a390af49b2cc5fd0563c5f4fa0c0485bb090d0)

Author SHA1 Message Date
Adrian Costina bef6a9c32c axi_ad9361: Split dma data into individual channels for both ADC and DAC 2014-06-07 17:15:31 +03:00
Adrian Costina 2837d788a6 mitx045: Added I2S core to the base design 2014-06-06 17:53:47 +03:00
Adrian Costina f217139770 fmcomms2: added project for mini_itx, xc7z045 version 2014-06-02 14:06:10 +03:00
Istvan Csomortani 1d53d79e25 fmcomms2/common: Fix ad9361's interface
Loopback the l_clk to clk. l_clk is the device sampling clock, clk is used to
    synchronize the cores in case of a multiple device configuration.
2014-05-21 10:09:54 +03:00
Istvan Csomortani 25e4520726 fmcomms2/common: Delet trailing white spaces 2014-05-21 09:47:37 +03:00
Rejeesh Kutty 51c0ee1e20 ml605: tcl updates 2014-05-06 09:29:21 -04:00
Rejeesh Kutty e7cbaca216 ml605: initial checkin 2014-05-05 11:24:12 -04:00
ATofan 5aac9d7288 FMCOMMS2 added sync option
Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
ATofan 9676146725 FMCOMMS2 AC701 Project
Not tested - must program Vadj on board
2014-04-01 15:35:44 +03:00
ATofan e597467447 FMCOMMS2 VC707 Project 2014-04-01 15:34:29 +03:00
ATofan 814b0d72d6 Modified Reset signals for FMCOMMS2 base design
Made all resets the same (sys_100m_resetn)
2014-04-01 15:32:48 +03:00
ATofan f8c1179bc1 FMCOMMS2 KC705 Project.
Added the files required for the FMCOMMS2 KC705 project.
Both DMA and DDS work.
2014-03-24 11:48:52 +02:00
ATofan 31a1ff384d FMCOMMS2 Base Design tcl modified
Added support for both Zynq and MicroBlaze projects
2014-03-21 09:57:52 +02:00
ATofan 2c898bf3a2 Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project
ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.
2014-03-18 15:27:42 +02:00
ATofan ee56db8d50 FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file
tcl: FCLK2 was modified from 100 MHz to 125 MHz.

xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz)
2014-03-14 16:27:56 +02:00
ATofan a6c3cb29c6 Modified SPI and ILA in fmcomms2_bd.tcl 2014-03-12 16:52:22 +02:00
Rejeesh Kutty 66c6b2b182 fmcomms2: added 2014-03-11 20:04:26 -04:00