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2 Commits (631f9253b27dc86507f66cc0b857fdbdd7b557fb)

Author SHA1 Message Date
Lars-Peter Clausen f181e037cc adrv9371x: zcu102: Fix QPLL feedback divider 
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
AndreiGrozav d05ed29212 adrv9371x_zcu102: Initial commit 2017-08-22 15:48:03 +03:00