5ffd1e1bac
common: a10soc: Fix gpio_bd_i constraints
...
Fix a copy and paste error and specify the IO_STANDARD for all gpio_bd_i
rather than twice for half of them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
53ca4f6ac9
arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
...
This fixes the bandwidth issue when data is streamed from the DDR and the system works at 61.44 MSPS
2017-07-28 10:11:55 +01:00
2abc7278bf
adrv9364z7020: Connect the gps_pps signal to the receiver
2017-07-28 08:08:27 +01:00
be5f2ad80f
adrv9361z7035: Connect the gps_pps signal to the receiver
2017-07-28 08:03:33 +01:00
31143cb893
arradio: Changed clock domain of the ADC and DAC path to half the interface clock
2017-07-27 13:40:41 +01:00
5a98e727f2
A10GX: Update DDR3 configuration
2017-07-27 12:38:14 +01:00
0aafd049c9
hdlmake.pl- remove ad_lvds
2017-07-26 10:32:44 -04:00
893af8d3e6
library & projects- ad_lvds/ad_data replace
2017-07-26 10:31:48 -04:00
d4820dd55a
library- remove ad_cmos_*
2017-07-26 10:20:39 -04:00
c15db8b74e
ad77681evb/zed: ad_lvds-ad_data replace
2017-07-26 10:18:26 -04:00
3eeba8273a
hdlmake.pl/fmcomms2- updates
2017-07-24 16:33:40 -04:00
eb113c8698
fmcomms2_kcu105: Initial commit
2017-07-24 18:45:48 +03:00
6e188d694d
ZCU102: SPI assign chip selects individually
...
Otherwise, Vivado 2016.4 sets all of the CSNs equal to CSN0. This fix is needed to get the FMCOMMS5 working properly on the ZCU102 (#36 )
2017-07-24 15:31:56 +01:00
fb557701a7
common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
...
Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the
same clock domain. They are both driven by the same clock. And even though
qsys is capable of detecting this it seems qsys interconnect is not able to
infer this and inserts a extra clock domain crossing bridge between the DMA
and the HPS AXI system memory interface.
To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so
that all components are driven by the same qsys clock signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:28:45 +01:00
374c49ff48
axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains
...
Qsys allows to query to query the clock domain that is associated with a
clock input of a peripheral. This allows to automatically detect whether
the different clocks of the DMAC are asynchronous and CDC logic needs to be
inserted or not.
Auto-detection has the advantages that the configuration parameters don't
need to be set manually and the optional configuration will be choose
automatically. There is also less chance of error of leaving the settings
in a wrong configuration when e.g. the clock domains change.
In case the auto-detection should ever fail configuration options that
provide a manual overwrite are added as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 16:06:37 +02:00
8b31fe73e0
hdlmake.pl updates
2017-07-21 10:37:56 -04:00
2d64d43475
ZCU102: SPI assign chip selects individually
...
Otherwise, Vivado 2016.4 sets all of the CSNs equal to CSN0. This fix is needed to get the FMCOMMS5 working properly on the ZCU102 (#36 )
2017-07-21 09:22:10 +01:00
a8ade15173
hdlmake.pl - updates
2017-07-20 15:11:21 -04:00
d132ed45cd
arradio- timing violations fix
2017-07-20 15:08:21 -04:00
669a2da735
common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
...
Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the
same clock domain. They are both driven by the same clock. And even though
qsys is capable of detecting this it seems qsys interconnect is not able to
infer this and inserts a extra clock domain crossing bridge between the DMA
and the HPS AXI system memory interface.
To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so
that all components are driven by the same qsys clock signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:27 +02:00
3ef00475bc
arradio/c5soc- clocking changes
2017-07-20 13:05:07 -04:00
f3ad2e24c1
rfsom2/ccbox- rtc int
2017-07-20 09:25:09 -04:00
8c60a2a850
rfsom/ccbox- rtc int
2017-07-20 09:22:45 -04:00
c11d7d9fda
rfsom2/ccbox- tsw s5 fix
2017-07-19 14:23:54 -04:00
d969b9ea9f
rfsom2/ccbox- tsw updates
2017-07-18 13:53:44 -04:00
becc3e8628
rfsom/ccbox- tsw updates
2017-07-18 13:51:37 -04:00
2e173201d4
daq2: daq2_qsys.tcl: Use sys_dma_clk
...
Use the sys_dma_clk clock module for clock and reset signals of the data
path, rather than using the A10GX specific sys_ddr3_cntrl signals. This
enables compatibility for all Altera/Intel platforms.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:38:20 +02:00
711cb66985
adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary
2017-07-14 10:20:57 +03:00
98cf18dd51
daq3/zc706: Fix system_top instantiation
...
Delete used interrupt ports: the ps_intr_10 and ps_intr_11 is used by
the jesd cores.
2017-07-06 13:29:09 +01:00
b4a25223fa
plddr3_dacfifo_bd: Increase the AXI burst length to max
...
Increase AXI burst length to maximum value, to support higher
data rates.
2017-07-06 10:15:06 +01:00
debca3a153
fmcjesdadc1: vc707: Remove unsed mb_intrs signal
...
The mb_intrs signal is never driven, it is a leftover of an earlier version
of the file, remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:38:25 +02:00
0360e8587e
Connect JESD204 interrupts
...
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
b0ebf2df06
daq3: Provide DAC JESD204 lane mapping
...
The DAQ3 does not use a 1-to-1 lane mapping for the DAC JESD204 link.
Provide the proper mapping when setting up the transceiver connections.
Without this the payload data will be mapped incorrectly and the
transmitted signals are scrambled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-30 16:01:10 +02:00
d65a543854
kc705: Fix ethernet address span
2017-06-30 14:23:01 +03:00
a765a9c709
arradio: Add i2c interface
2017-06-29 17:26:58 +03:00
6ebef5dde0
make: Update make files
2017-06-26 15:51:19 +01:00
ca12938873
ad77681evb: Suppress a critical warning
2017-06-22 14:25:43 +01:00
1541943ff2
adrv9371_alt: Delete the fifos from the RX path
...
+ Delete the rx_fifo and rx_os_fifo from the RX datapath
+ Change the receive DMA's source interface type to wr_fifo
2017-06-22 11:58:10 +01:00
2e8be3d7a6
daq2: Provide DAC lane map
...
Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
4bf5990451
adi_board.tcl: ad_xcvrcon: Add lane mapping support
...
Add a parameter to the ad_xcvrcon function that allows to provide a mapping
between logical and physical lanes. By default if no lane map is provided
the logial and physical lanes are mapped 1-to-1. If a lane map is provided
logical lane $n is mapped onto physical lane $lane_map[$n].
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
56867b362e
daq3- updated to 12.5G
2017-06-16 09:02:26 -04:00
3fb5408acc
fmcjesdadc1/a10gx- fix sysref, lvds io and such
2017-06-15 13:57:21 -04:00
6ec9eab7b9
fmcjesdadc1/a10soc- fix sysref, lvds io and such
2017-06-15 13:57:21 -04:00
ef290ef484
hdlmake.pl updates
2017-06-15 11:42:44 -04:00
e33e6a84f4
a5gt/a5soc - removed
2017-06-15 11:41:28 -04:00
a23fb793a0
a5gt/a5soc - removed
2017-06-15 11:40:58 -04:00
2649458b6d
hdlmake.pl updates
2017-06-15 10:21:57 -04:00
fd0c7f1b1c
usdrx1/a10gx- updated to a10gx
2017-06-15 10:21:57 -04:00
0311ed411c
usdrx1/a10gx- added
2017-06-15 10:21:57 -04:00
7ac083b932
fmcjesdadc1/a10soc- sysref fixes
2017-06-15 10:15:59 -04:00
004aee930b
fmcjesdadc1/a10gx- fix sysref, gpio connections
2017-06-14 14:40:23 -04:00
dba419239b
hdlmake.pl updates
2017-06-14 10:41:14 -04:00
3299d244fe
fmcjesdadc1: a10gx/a10soc
2017-06-14 10:39:57 -04:00
38c708d4d0
fmcjesdadc1: a10gx/a10soc
2017-06-14 10:39:38 -04:00
051c1d6644
fmcjesdadc1: a10soc
2017-06-13 15:00:22 -04:00
c1bc1259a7
fmcjesdadc1: a10gx
2017-06-13 12:39:45 -04:00
3f3ea5f99a
hdlmake.pl- updates
2017-06-13 09:55:08 -04:00
ffb6cd4b0b
scripts- add a5soc device
2017-06-13 09:54:01 -04:00
ff646b0cfc
common/a5soc- alt 16.1 updates
2017-06-13 09:54:01 -04:00
0eacde9158
fmcjesdadc1/a5soc- alt 16.1 updates
2017-06-13 09:54:01 -04:00
6decba3c3b
hdlmake.pl updates
2017-06-09 16:23:17 -04:00
74f9a99655
fmcjesdadc1/a5gt- altera 16.1 updates
2017-06-09 16:20:49 -04:00
2e17e67627
common/a5gt- altera 16.1 updates
2017-06-09 16:20:15 -04:00
688758e6c6
scripts/adi_project_alt- add a5soc, a5gt
2017-06-09 16:19:29 -04:00
ca536d50ac
altera 16.1 c5soc updates
2017-06-08 15:03:03 -04:00
f3af192f30
altera 16.1 arradio updates
2017-06-08 15:02:46 -04:00
ca20309166
adi_project_alt: add c5soc
2017-06-08 15:02:24 -04:00
b8a75a7285
hdlmake.pl - updates
2017-06-07 10:23:20 -04:00
6100a697e8
daq3/a10gx- alt 16.1 updates
2017-06-07 10:23:20 -04:00
40bfd0380e
adrv9371x/a10gx- alt 16.1 updates
2017-06-07 09:19:14 -04:00
83747ddb33
ad77681evb: Fix IO constraints
2017-06-07 14:28:39 +03:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
d1bab7ddb9
hdlmake.pl- updates
2017-06-06 16:10:05 -04:00
3f92381bd0
daq2/a10gx- project/constraint updates
2017-06-06 16:09:15 -04:00
dd48929327
hdlmake.pl - updates
2017-06-06 12:25:35 -04:00
5176e427a1
common/a10soc- add project create tcl procedure
2017-06-06 12:24:13 -04:00
f278b6e6c9
adrv9371x/a10soc- constraints/project updates
2017-06-06 12:23:26 -04:00
e34057c2b2
adrv9371x/a10gx- constraints/project updates
2017-06-06 12:22:31 -04:00
e9c49f667f
altera- 16.1.2 & a10soc
2017-06-06 12:20:44 -04:00
578ccaaa44
adrv9371x:a10gx, update create project command and Makefile
2017-06-06 17:30:12 +03:00
54a53c015a
scripts: changed adi_project_create command to adi_project_altera
2017-06-06 17:29:12 +03:00
0d99aa02e1
m2k: Updated project to work with the fifo_depth related changes
2017-06-06 15:37:23 +03:00
491602d88b
make: Update make files
2017-06-06 12:00:40 +03:00
6df97a61ae
adrv9364z7020- fix enable/en_agc mixup
2017-06-05 16:06:27 -04:00
eadbf9ae30
altera- remove default assignments from procedure
2017-06-05 15:25:38 -04:00
0bd22e78d9
altera- adi-project-create version
2017-06-05 15:24:35 -04:00
1b1c7ffa61
adi_project- altera version
2017-06-05 15:13:21 -04:00
50cdb6db67
Merge branch 'jesd204' into dev
2017-05-31 20:44:32 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
2d56141bbd
altera- 2017-r1 16.1.2
2017-05-30 12:21:27 -04:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
669e0a01d0
fmcomms2/a10gx: Remove project
2017-05-26 17:05:55 +03:00
3c47d00a96
daq1/a10gx: Remove project
2017-05-26 17:05:28 +03:00
414943db4b
m2k: Fix Make files
2017-05-26 09:54:08 +03:00
c4fa41e4e5
adrv9364z7020: Update README
2017-05-25 17:47:58 +03:00
3af00dc520
adrv9361z7035: Update README
2017-05-25 17:47:19 +03:00
9ecfcce4ec
adrv9364z7020: Rename pzsdr1 to adrv9364z7020
2017-05-25 17:20:23 +03:00
26822af7e1
adrv9361z7035: Rename pzsdr2 to adrv9361z7035
2017-05-25 17:17:54 +03:00
4c998d1e18
make: Update make files
2017-05-25 15:12:17 +03:00
f9057b1825
m2k: Add scale correction option. Update parameters
2017-05-24 15:59:24 +03:00
4d00439d52
fmcomms11: Convert to ADI JESD204
...
Convert the FMCOMMS11 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
d4c9f1e9f1
fmcjesdac1: Convert to ADI JESD204
...
Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
9a917ae8bf
fmcadc4: Convert to ADI JESD204
...
Convert the FMCADC4 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
bbe457acea
fmcadc2: Convert to ADI JESD204
...
Convert the FMCADC2 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
a38bbb7eb4
daq3: Convert to ADI JESD204
...
Convert the DAQ3 project to the ADI JESD204 link layer cores. The change is
very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
0ec92d3153
daq2: Convert to ADI JESD204
...
Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is
very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
a7e72245ff
adrv9371: Convert to ADI JESD204 core
...
Convert the ADRV9371 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
5ca79e843c
ad6676evb: Convert to ADI JESD204
...
Convert the AD6676EVB project to the ADI JESD204 link layer core. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
0a72693d4d
adi_board.tcl: ad_xcvrcon: Handle ADI JESD204 core
...
Let the ad_xcvrcon handle the ADI JESD204 link layer cores. The function
will detect the JESD204 core vendor and connect the appropriate signals
based on it. This means it can still be used with the Xilinx JESD204 core
as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
9e8d35b6e6
adi_board.tcl: ad_cpu_interconnect: Handle hierarchies
...
When trying to use ad_cpu_interconnect to connect to a AXI interface that
is a outer port of a hierarchy this will fail at the moment as it kind find
the matching clock and reset signals.
Add support for traversing into the hierarchy and find the final target AXI
port inside the hierarchy. Then find the matching clock and reset and
traverse them back the corresponding hierarchy outer ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
01aea161fa
Create CDC helper library
...
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
3db1050e91
pzsdr2/ccfmc: enable eth1 mdio
2017-05-22 13:38:36 -04:00
f09b902609
usdrx1- spi/mlo fixes
2017-05-22 13:22:44 -04:00
12930c8470
motcon2_fmc: Explicitly assign ETH0 MDIO to EMIO
2017-05-22 18:53:00 +03:00
0eaa98370e
fmcadc2/vc707- spi clock reg can't be on iob
2017-05-19 15:22:33 -04:00
eb7171e212
daq3/kcu105- reorder refclk constraints
2017-05-19 11:41:45 -04:00
36037a76f8
kcu105- vivado now depends on order of constraints?
2017-05-19 11:21:36 -04:00
0b3b1e6c76
kcu105- remove ethernet delay ctrl false path
2017-05-19 11:21:36 -04:00
e033d6c48e
m2k: Refresh Makefile
...
The util_cpack core is currently not used by the M2K project. Refresh the
Makefiles to reflect this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
f3959cb5b9
zcu102- 2016.4 updates
2017-05-18 14:17:20 -04:00
4f0accbbfa
adrv9371x fix dacfifo name
2017-05-18 12:54:14 -04:00
d507cd0c9a
quartus optimization for frequency
2017-05-18 11:34:29 -04:00
ff7dc41066
alt-jesd- constraints update
2017-05-18 09:55:24 -04:00
d10faabc3f
a10soc- 16.1- hsp sdram reset
2017-05-17 16:30:37 -04:00
f8f7bdd6a6
a10soc- fix version check
2017-05-17 16:26:28 -04:00
70e3dd00ff
scripts: Update required tool versions
2017-05-17 16:45:20 +03:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
c4b4bdc415
daq2/a10gx- constraints remove 16.0
2017-05-16 10:09:42 -04:00
cfcb269d38
a10gx- change ddr to 1G
2017-05-15 09:32:36 -04:00
63b701ccab
altera- add version check
2017-05-12 15:13:29 -04:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
ecfa15bfce
version check- change to critical warning
2017-05-12 09:51:48 -04:00
039ae9ae92
fmcadc5- syntax/port name fixes
2017-05-10 16:30:15 -04:00
6a0a2e4661
hdlmake.pl updates
2017-05-10 14:35:06 -04:00
74c44cf830
axi_fmcadc5- remove pack-driver is too late
2017-05-10 14:33:56 -04:00
0e5a24ee7c
axi_fmcadc5_sync- raw inputs & constraint fixes
2017-05-08 10:30:51 -04:00
6387b53266
ad77681evb: Initial commit
2017-05-04 12:19:11 +03:00
ef97c1e375
adrv9371x/a10soc: Fix constraints
...
Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 14:37:11 +03:00
f0bc3e20ef
zcu102: Automatic IP version update fix
2017-05-02 12:52:43 +03:00
cd8f4f23be
zcu102: Automatic IP version update
2017-05-02 12:30:00 +03:00
d6b09602ed
usrpe31x: Automatic IP version update
2017-05-02 12:27:57 +03:00
485c810c2c
pzsdr*: Automatic IP version update
2017-05-02 11:43:32 +03:00
b3ce821311
change pl ddr clock to 1G
2017-05-01 09:35:10 -04:00
d29f420ffa
axi_fmcadc5_sync: add a calibration signal generation
2017-04-28 11:13:24 -04:00
7a53b99b8b
daq2: zc706: Increase DAC FIFO size
...
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.
In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 12:29:01 +02:00
f6eea23f5e
adaq7980: Update tcl command for IP configuration
2017-04-28 10:12:33 +03:00
353d1d44da
ad5766_sdz: Update tcl commands for IP configuration
2017-04-28 10:12:05 +03:00
956753ca9c
hdlmake- updates
2017-04-27 15:11:01 -04:00
68fc5c89a7
fmcadc5- remove stand alone psync
2017-04-27 15:09:56 -04:00
75c7525c60
fmcadc5- remove psync module
2017-04-27 13:29:06 -04:00
2027c8427c
adi_boadr- disconnect and remove unused ports
2017-04-27 13:26:17 -04:00
902eaaaf4c
fmcadc5- sync updates
2017-04-27 13:26:17 -04:00
0442e7d404
util_adxcvr: Fix parameter setup at instantiation
...
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
2017-04-27 15:35:39 +03:00
8aa8d3a0e5
ad5766_sdz/zed: Fix i_iobuf_reset width
2017-04-27 11:28:26 +03:00
4836aa2179
adaq7980/zed: Update Makefile
2017-04-27 11:28:25 +03:00
fbccb377cc
adaq7980: Add an trigger generator for SPI offload
2017-04-27 11:28:23 +03:00
63cab50872
adaq7980_sdz: Initial commit
...
The device is interfaced with a SPI Engine, the PD lines are controlled
by GPIOs.
2017-04-27 11:28:23 +03:00
ccc4aac505
ad5766_sdz: Fix the PIN assignment
2017-04-27 11:27:34 +03:00
8213d8a916
cn0363: Update block design
...
Configure the interconnect and offload modules inorder to activate
its interfaces. In the past, these interfaces did not have any
parameter dependencies, so this configuration were not required.
2017-04-27 11:27:33 +03:00
a6146393be
ad5766_sdz: Fix DMA data path
2017-04-27 11:22:32 +03:00
a2c20551a2
axi_ad5766: Add Makefiles for the core
2017-04-27 11:22:31 +03:00
f5fba79a08
ad5766_zed: Add an IOBUF to the reset line
2017-04-27 11:21:14 +03:00
9de0fe56d9
ad5766: Integrate the new axi_ad5766 into the project
2017-04-27 11:21:14 +03:00
d177827224
ad5766_sdz : Fix SPI interface connection
2017-04-27 11:16:23 +03:00
225d133a68
ad5766_sdz: Initial commit
2017-04-27 11:12:45 +03:00
cfd4e006b3
hdlmake updates
2017-04-25 15:46:26 -04:00
8fba8295f0
fmcadc5- hdl sync handling
2017-04-25 15:44:40 -04:00
68bb7ffa40
adi_board- keep port delete simple
2017-04-25 15:44:03 -04:00
8eb65186e9
cn0363: Reorder the configuration settings of the fir filters
...
It seems that there are some dependencies between the fir compiler
cores parameters. With the old order of the parameter settings,
the tool throws the following warning:
CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES
does not match between /processing/sequencer/i_q_filtered(4)
and /processing/lpf/M_AXIS_DATA(5)
2017-04-25 17:40:09 +03:00
a6457cb54f
m2k:standalone, remove power optimizations as they are performed manually
...
- testing shows that the actual power consumtion is a bit less with them turned off
2017-04-25 10:09:55 +03:00
b92703b59f
daq2: Fix typo
2017-04-24 15:44:45 +03:00
0cfef974a6
cn0363: Fix typos and mistakes made in 0737183
2017-04-24 12:43:33 +03:00
b9bc85dd1a
daq2/zcu102: Update tcl command for IP configuration
2017-04-24 11:51:12 +03:00
871cfa7e5b
daq2/kcu105: Update tcl command for IP configuration
2017-04-24 11:50:35 +03:00
49f096dc71
daq1: Fix typo
2017-04-24 11:49:08 +03:00
4e77acf282
adv7511/kcu105: Update tcl command for IP configuration
2017-04-24 11:48:33 +03:00
216826a9e5
adv7511: audio_clkgen: Disable clock source buffer insertion
...
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.
For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer. So set the
configuration accordingly.
Avoids the following warning:
[Opt 31-32] Removing redundant IBUF since it is not being driven by a
top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
Resolution: The tool has removed redundant IBUF. To resolve this
warning, check for redundant IBUF in the input design.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 14:21:27 +02:00
4a582bf9ad
adv7511: audio_clkgen: Disable phase alignment
...
There is no need for the audio clock to be phase aligned to its source
clock. When phase alignment is disabled the MMCM uses an internal feedback
path without requiring external resources, so disable it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 14:21:27 +02:00
76e4105bfd
adv7511: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 14:21:27 +02:00
a12adf9f02
adv7511: audio_clkgen: Disable unused pins
...
Neither the reset nor the locked signal is used in this design, so disable them. Avoids warnings about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 14:21:27 +02:00
74687eb88b
fmcomms7: Update IP instantiations
2017-04-21 15:12:01 +03:00
5174bc1f67
fmcomms11: Update IP instantiations
2017-04-21 15:11:25 +03:00
c9eaa43b1e
fmcomms5: Update UP instantiations
2017-04-21 15:10:44 +03:00
bb0cdf2f5e
fmcomms2: Update IP instantiations
2017-04-21 15:09:37 +03:00
95249d2165
fmcjesdadc1: Update IP instantiations
2017-04-21 15:08:16 +03:00
4eaa43f8e1
daq3: Update IP instantiations
2017-04-21 15:07:41 +03:00
1ae357ce10
daq1: Update IP instantiations
2017-04-21 15:06:40 +03:00
073718315a
cn0363: Update IP instantiations
2017-04-21 15:06:06 +03:00
fa794520fd
kc705_common/adv7511: Update IP instantiations
2017-04-21 15:03:31 +03:00
0e6cc95d0d
pzsdr1/pzsdr2: audio_clkgen: Disable clock source buffer insertion
...
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.
For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer. So set the
configuration accordingly.
Avoids the following warning:
[Opt 31-32] Removing redundant IBUF since it is not being driven by a
top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
Resolution: The tool has removed redundant IBUF. To resolve this
warning, check for redundant IBUF in the input design.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 13:22:33 +02:00
95a46bf1e1
pzsdr1/pzsdr2: audio_clkgen: Disable phase alignment
...
There is no need for the audio clock to be phase aligned to its source
clock. When phase alignment is disabled the MMCM uses an internal feedback
path without requiring external resources, so disable it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 13:22:33 +02:00
cfc51016ea
pzsdr1/pzsdr2: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 13:22:19 +02:00
6ed721ee66
adrv9371/a10soc: Integrate the avl_dacfifo into project
2017-04-21 13:27:35 +03:00
2379514ae6
ac701_common/adv7511: Update IP instantiations
...
IPs are instantiated using the ad_ip_instance process, and configured
with the ad_ip_paramter process, to facilitate the tool upgrade.
2017-04-21 13:16:25 +03:00
6d72ce800c
m2k: zed: Fix default HDMI clock frequency
...
The input clock frequency of the axi_clkgen was changed from 200 MHz to
100 Mhz. Update the divider settings accordingly to keep the standard
default output frequency of 148.5 MHz.
The incorrect divider settings did not affect operation of the design since
software reprograms them at startup anyway, but changing them avoids the
following warning:
[DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for cell i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/i_mmcm. The computed FVCO is 445.455 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 49.000, CLKIN1_PERIOD = 10.00000, and DIVCLK_DIVIDE = 11 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).
This violation may be corrected by:
1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run. Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range.
2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range.
3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range.
4. The MMCM configuration may be dynamically modified by use of DRP which is recognized by an ACTIVE signal on DCLK pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 20:36:34 +02:00
bb0021a926
common: zed/zc702/zc706/mitx045: audio_clkgen: Disable phase alignment
...
There is no need for the audio clock to be phase aligned to its source
clock. When phase alignment is disabled the MMCM uses an internal feedback
path without requiring external resources, so disable it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
bfcc3696e4
common: zed/zc702/zc706/mitx045: Set audio clkgen clock source type
...
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.
For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer. So set the
configuration accordingly.
Avoids the following warning:
[Opt 31-32] Removing redundant IBUF since it is not being driven by a
top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
Resolution: The tool has removed redundant IBUF. To resolve this
warning, check for redundant IBUF in the input design.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
23ccc66f22
common: zc702/zc706/mitx045: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
806947444f
ad9434_fmc: Port redeclaration as a wire is not allowed
2017-04-20 14:33:47 +03:00
0ffbe50163
m2k: zed: Run video DMA at higher clock rate
...
For the M2K standalone version we run the interface clock at a lower rate
to reduce the power consumption. While this is not necessary on the ZED
board we also run the interface at a lower rate for consistency.
Currently the video DMA on the ZED board uses the interface clock for the
data path as well. This is now too slow to support 1080p@60Hz so move it
over to a faster clock.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 16:29:09 +02:00
b213567305
common: zed: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 16:29:09 +02:00
1d4b92190a
fmcomms2/zc702: Fix Warning[Synth 8-2611]
...
In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
2017-04-19 13:54:03 +03:00
8e6dbe1917
fmcadc5/vc707, lpm mode
2017-04-18 12:41:53 -04:00
ddfbdfd2f7
pzsdr1/pzsdr2- ccbox added tws
2017-04-18 11:37:23 -04:00
5a7aa80145
m2k: zed, cleaned up some warnings
2017-04-18 17:17:11 +03:00
919010e85f
m2k: ip automatic version update
2017-04-18 15:12:07 +03:00
b05505a1c3
m2k: Move the BRAM generation outside of the variable fifo IP
2017-04-18 12:17:40 +02:00
5f83e20d33
m2k: standalone: Rework PS7 clocking
...
At the moment the PS7 is using three PLLs to generate its clocking tree.
One for the DDR, one for the ARM and one for the IO. This allows to run all
components at their respective maximum clock and extract maximum
performance from all components.
With some slight modifications it is possible to trade maximum performance
for a reduction in power consumption by using the same PLL for all three
sets of components and disabling the other two PLLs.
The CPU is now running at 500MHz rather than 666MHz and the DDR memory at
500MHz rather than 533MHz. This reduces power consumption by ~125mW.
This is OK since neither of them is a bottleneck for overall system
performance.
In addition software will downclock the CPU to 250MHz when full performance
is not required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
3b748d8252
m2k: standalone: Disable 200MHz clock
...
The 200 MHz clock was only used as the IODELAY controller clock. Since the
design does not use any IODELAYs anymore this clock can be removed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
63dfec25c1
m2k: standalone: Disable 2nd PS7 reset port
...
This reset is not used in the design, so remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
189e9194c8
m2k: Standalone, enabled power optimization
2017-04-18 12:17:40 +02:00
8b76c34dea
scripts: Created ADI_POWER_OPTIMIZATION parameter for enabling power optimizations in the implementation stage
2017-04-18 12:17:40 +02:00
07e52b4566
m2k: Connect logic_analyzer path to clk_out instead of clk
...
- this allows for the clock switching to be done inside axi_logic_analyzer core
2017-04-18 12:17:39 +02:00
610cc3affa
m2k: standalone: Disable DMA debug registers
...
The debug register logic for the DMA take up a fair amount of resources.
Disabling them frees up space in the FPGA and also helps a bit with power.
Since those registers are mainly useful in development and not so much in
production the change shouldn't have any visible external effects.
It is possible to re-enable the debug registers by setting DEBUG_BUILD=1.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
c9f863f189
m2k: standalone: Set static switching activity for the reset signals
...
The global reset signals are only asserted for a short moment during system
startup and deasserted during normal operation, which is the case we care
about for power analysis. Giving them a static switching probability
indicating that they are always de-asserted will yield better results for
power analysis.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
b206f8f37a
m2k: Disable AD9963 core RX datapath again
...
The RX datapath has a lot of things (IQ correction, DC filter, ...) that
take up a lot of space which are all not really needed in this project. So
disable the RX datapath.
It was previously enabled because the ad9963 core did not perform
sign-extension on the ADC data signal when the datapath was disabled. But
this has now been addressed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
c1ba57f808
m2k: Rework clocking domains
...
At the moment the register map fabric and DMA system memory side are
clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot
faster than the clock has to run. There are only a few 100 register map
accesses per seconds at most and they are not on timing critical paths. The
penalty from clocking them at a lower rate is negligible for the overall
system performance.
The maximum clock rate for the DMAs is determined by the throughput
requirements. This is 200 Mbytes/s for the logic analyzer, pattern
generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA.
The DMA datapath width is 64-bit so the required clock rates are 25MHz and
50MHz respectively. Some headroom is required to accommodate for occasional
bubble cycles on the data bus and the difference in reference clocks for
the converter and processing system.
The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the
ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is
introduced.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
2eaf931e07
m2k: Replace logic analyzer MMCM
...
The MMCM generating the logic analyzer clock unfortunately consumes a
disproportionately large amount of power compared to the rest of the
design.
Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs.
The IO PLL is running anyway so the power requirement is much lower.
For the time being this means we loose the ability to source the clock from
an external pin. But that feature is not supported by software at the
moment anyway. We'll bring it eventually when required.
This changes reduces power consumption by roughly 100mW.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
e616c8da0b
m2k: Remove channel pack core for now
...
We always have both ADC channels enabled and the cpack core takes up a fair
amount of space, so remove it for now. Might come back later when we really
need it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
efa2d0c006
m2k: Connected adc/dac resets to decimation/interpolation cores
2017-04-18 12:17:39 +02:00
500112f79b
m2k: Renamed l_clk to adc_clk and rst to adc_rst
2017-04-18 12:17:39 +02:00
6a49aefb6c
m2k: Updated project to use new tx path with serdes
2017-04-18 12:17:39 +02:00
b58a5c37eb
m2k: Reduce AXI interconnect utilization
...
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
71394ee465
kcu105: ip automatic version update
2017-04-18 11:59:54 +03:00
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
8e0c87e089
pluto: cleaned up some warnings
2017-04-18 10:34:13 +03:00
f3c0be0868
motcon2_fmc: cleaned up some warnings
2017-04-18 10:33:13 +03:00
6e14cdb5f4
cftl_std: cleaned up some warnings
2017-04-18 10:32:28 +03:00
d585d65692
cftl_cip: cleaned up some warnings
2017-04-18 10:29:20 +03:00
20672a3a8b
mitx045: ip automatic version update
2017-04-14 17:46:25 +03:00
954037a716
microzed: ip automatic version update
2017-04-14 17:24:24 +03:00
ebc04bcd9c
usdrx1: ip automatic version update
2017-04-14 17:16:35 +03:00
24b797f1a6
motcon2: ip automatic version update
2017-04-14 17:11:08 +03:00
4981e6e525
usb_fx3: ip automatic version update
2017-04-14 16:55:30 +03:00
c419b0042b
pluto: ip automatic version update
2017-04-14 16:55:07 +03:00
79174422b6
imageon: ip automatic version update
2017-04-14 16:54:42 +03:00
4bda0c3a1a
cftl_cip: ip automatic version update
2017-04-14 16:54:07 +03:00
afe8b071a3
cftl_std: ip automatic version update
2017-04-14 16:53:10 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
04a4001dba
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 19:03:16 +03:00
627f78ec19
Ip automatic version update: common/board
...
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
6d2b3bc1c7
adi_project- try something simple first
2017-04-11 14:27:35 -04:00
1d9a8a24dc
adi_board- create_bd_cell replacement
2017-04-11 14:26:02 -04:00
bc9483c5a2
Ip automatic version: Update ad*/common/ad*_bd.tcl
...
ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
454e6c0382
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:53 -04:00
2535165461
xilinx- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:19 -04:00
80f93e6a31
zc706- ad-ip-instance & ad-ip-parameter
2017-04-06 13:03:22 -04:00
820874ef93
adi_board- add auto ip version handling
2017-04-06 13:02:17 -04:00
e04793b6eb
m2k: standalone: Assign 0 to unused GPIO inputs
...
To avoid warnings from the tools assign 0 to the unused GPIO inputs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:16:25 +02:00
8eb1dd0a8b
adrv9371x/altera- xilinx/chip-select consistency
2017-03-29 12:59:09 -04:00
24a7d8ea9d
m2k: Remove redundant s_axi_{aclk,aresetn} assignment
...
ad_cpu_interconnect will make sure to connect the clock and the reset of
the AXI interface. Remove the redundant manual assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-28 11:14:48 +02:00
deb8635854
adrv9371x/altera- gpio equivalency fix
2017-03-27 16:37:55 -04:00
8f1564a9c4
adrv9371x/a10gx- gpio matching
2017-03-27 13:51:45 -04:00
ae0f4672b2
daq1/a10gx- fix project to compile
2017-03-23 09:46:40 -04:00
cc6bf53d98
adrv9371x/a10soc- altera reset synchronizer false path?
2017-03-23 09:46:40 -04:00
968d94603e
fmcjesdadc1: Update xcvr configuration to the default one used for this board
2017-03-23 11:31:00 +02:00
4a275302a0
a5soc- add ddr3 location assignments
2017-03-22 10:12:34 -04:00
7e87ecae22
altera/a10gx- daq1/fmcomms2 fix typos
2017-03-22 09:48:02 -04:00
b3f06af77a
altera srf files do not work
2017-03-22 09:25:50 -04:00
66a5d44a18
a5gte- add constraints for tq
2017-03-21 10:53:31 -04:00
2e22ce3b62
a10gx- ignore preliminary timing model warnings
2017-03-21 10:52:28 -04:00
d84e34fe5f
arradio/c5soc- reset false path for vga dma
2017-03-21 10:15:38 -04:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
c7351f3ce3
arradio/c5soc- remove qsys files
2017-03-20 15:56:07 -04:00
589e6b53d8
arradio/c5soc- qsys-script flow
2017-03-20 15:42:33 -04:00
b39fecadd9
altera- ignore preliminary timing messages
2017-03-20 12:48:53 -04:00
7dfa8c599f
arradio/c5soc- updated to new framework/16.0
2017-03-20 12:15:18 -04:00
12f44ccbcc
arradio/c5soc- critical warnings fix
2017-03-20 12:14:21 -04:00
9b6dd27c23
ad9361- delay initialization
2017-03-15 12:06:59 -04:00
09bcecb6ed
m2k: Simplify DMA connection to HP1
2017-03-15 15:11:30 +02:00
2a9b3cea09
m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use
2017-03-14 13:57:50 +02:00
f7c2bd943b
m2k: Enable AD9963 adc data path processing.
...
- part of the path is the sign extension module. Without it, the triggering doesn't work correctly
2017-03-13 23:18:29 +02:00
c3c8c366d3
axi_ad9361- add receive init delay
2017-03-13 16:28:53 -04:00
dac75f79ab
fmcomms5/usrpe31x- add iodelay report
2017-03-10 13:38:27 -05:00
1b3f752c3d
pzsdr1/pzsdr2/pluto- add iodelay report
2017-03-10 12:55:22 -05:00
0ae79ca7ac
move/rename - delay script belongs to ad9361
2017-03-10 12:44:32 -05:00
e736504e0f
fmcjesdadc1, usdrx1: Using the same clock in rx_data path
2017-03-10 14:26:51 +02:00
d08d1d5a1b
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
2017-03-10 14:20:42 +02:00
452e5e5ce0
fmcomms2- add delay reporting for iodelay
2017-03-09 15:29:15 -05:00
8bdfbe2b0a
fmcomms2- report delays
2017-03-09 15:21:42 -05:00
7e5d8664ad
fmcjesdadc1_a5gt: rx_data pins are all associated to the same clock
2017-03-09 08:57:03 +02:00
0e002f2f31
daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-09 08:50:55 +02:00
191669ad28
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 16:13:46 +02:00
fc8af6903f
pzsdr2/ccfmc- add rf input protection
2017-03-06 16:19:55 -05:00
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
38a27d02f6
a10soc/plddr4- differential refclk
2017-03-06 14:11:36 -05:00
936c441763
adrv9371x- dacfifo bypass-gpio control
2017-03-06 10:35:09 -05:00
762276a880
adrv9371x- dacfifo changes
2017-03-06 10:33:52 -05:00
4a6fe54fcf
daq2_common: Update common scripts
...
Add new port connection for util_dacfifo
2017-03-03 18:49:10 +02:00
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
bc6a09c828
adrv9371x/a10soc- dacfifo added
2017-03-01 15:35:04 -05:00
5b5c0dde99
ad6676evb: Set default xcvr parameters to common design
2017-03-01 11:32:17 +02:00
b78e9d8c27
daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
0cc5130c9a
adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
c1be17a3af
Altera a10 devices: disable warnings regarding unused channels
2017-03-01 11:32:17 +02:00
dc168f41fe
adrv9371_a10soc: Fixed port assignments
2017-03-01 11:32:17 +02:00
aad41039bd
a10soc- plddr4 settings
2017-02-28 13:36:28 -05:00
59dda01419
m2k: Disabled DDS cores for the generic project
2017-02-28 10:10:28 +02:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
19c7b5d340
fmcadc5- move adc fifo settings to system-board
2017-02-27 16:06:39 -05:00
c1aac4a9fb
common: adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
545e458997
m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage
2017-02-27 14:17:29 +02:00
eda585f0e4
m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2
2017-02-27 14:16:32 +02:00
908da60ab6
m2k: zed, changed constraints so they are the same with the ZED default configuration
...
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
2017-02-27 14:13:34 +02:00
0059c907ea
adrv9371: Drive the TX DMA interface with sys_dma_clk
2017-02-24 15:50:12 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
b00dc4b195
plddr3- change to board files
2017-02-22 15:22:50 -05:00
89b49d2f67
fifo- as board files
2017-02-22 15:18:50 -05:00
879ed64bb6
compression flag changes
2017-02-22 15:15:53 -05:00
8a5e2ff46e
sys_wfifo- removed
2017-02-22 15:13:18 -05:00
754ac6a403
w/r-fifo- removed
2017-02-22 15:10:06 -05:00
040b61de60
fmcadc5: Updated default parameters
2017-02-20 17:13:58 +02:00
a15e05c497
adcfifo- remove axi-byte-width parameter
2017-02-17 15:29:10 -05:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
e8bcbb74da
scripts: fixed tcl syntax for altera projects not meeting timing
2017-02-16 21:21:51 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
8453d758c2
scripts: If an altera project doesn't meet timing, rename the sof
2017-02-16 19:20:49 +02:00
343d0472d4
fmcadc2: Move GT setting to common/system_bd.tcl
2017-02-16 14:56:25 +02:00
07184b31d2
fmcadc2: Define default clock selection for Xilinx GTs
2017-02-16 12:35:24 +02:00
86c279c238
pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix critical warnings
2017-02-14 14:51:49 +02:00
46290193f3
pzsdr2: ccusb, renamed clk_out to clkout_in
2017-02-14 11:58:11 +02:00
27119343f2
pzsdr2: ccusb, connect unused clock pins to GND
2017-02-14 11:56:54 +02:00
fa37f4dd0a
pzsdr2: Don't set a disabled parameter
2017-02-14 11:56:08 +02:00
6a9b7580de
pzsdr1: ccusb, renamed clk_out to clkout_in
2017-02-14 11:54:46 +02:00
acef0113d1
pzsdr1: ccusb, connect unused clock pins to GND
2017-02-14 11:50:37 +02:00
46883731eb
pzsdr1: Don't set a disabled parameter
2017-02-14 11:50:06 +02:00
a569b6bf0c
pluto: Interpolation, connect fifo_rd_valid to s_axis_data_tvalid
2017-02-13 18:08:52 +02:00
e215a091b2
m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints
2017-02-13 12:02:59 +02:00
4e62fb0ef3
m2k: Add reset circuitry on the logic_analyzer clock domain
2017-02-13 12:02:11 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
f5f1f47691
ad9467_fmc: Delete asynchronous clock group definition
...
This is a very bad way to handle timing. All the false path
should be defined explicitly, rather than define asynchronous clock
domains.
2017-02-10 16:21:35 +02:00
c39ed08edd
zcu102/*- actual clock == desired clock
2017-02-06 12:53:47 -05:00
58872aa3ef
fmcomms2/zc706pr- prcfg is a single clock synchronous design
2017-02-06 10:59:18 -05:00
971bcbb0fc
fmcomms1: Remove project
2017-02-03 16:42:44 +02:00
096274a033
daq2/zcu102- fix refclock pin swap
2017-02-03 09:26:07 -05:00
7c363cd5a7
daq3/a10gx/system_constr.sdc- fix typo
2017-02-03 09:26:07 -05:00
35f660fe06
fmcjesdadc1/vc707- constraint clean-up
2017-02-02 15:05:49 -05:00
d46352928a
fmcomms5- fix ovf net connections
2017-02-02 14:24:06 -05:00
6aadb49e80
m2k: Remove use board flow from the standalone version
2017-02-02 12:58:58 +02:00
0d0c3e99fd
m2k: Added I2C pull-ul, removed SLEW constraints
2017-02-02 12:35:46 +02:00
85ff496c12
daq2/a10gx- gpio match with others
2017-02-01 20:54:56 -05:00
5155b3f46d
m2k: Fix gpio buswidth
2017-02-01 17:43:01 +02:00
cfff70d358
M2K: Update standalone project
...
- configured PS7 similar to pluto. Added specific constraints instead of default PS7
- moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1]
2017-02-01 14:27:11 +02:00
6bdd853b88
m2k: Updated PS7 configuration
2017-01-31 23:08:53 +02:00
b14d740f87
M2K: initial commit
2017-01-31 16:43:40 +02:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
97d72d2f65
a10gx- xilinx/altera sync-up
2017-01-30 10:01:28 -05:00
b14e7fe4ee
daq3/kcu105- 1.25GSPS
2017-01-30 10:01:28 -05:00
48ad24cdbe
enable partial reconfiguration mode
2017-01-27 09:26:53 -05:00
be1328c55b
kcu105- added missing ethernet configurations
2017-01-23 10:14:09 -05:00
661413627f
daq3- round about way to avoid ip getting locked
2017-01-20 15:55:33 -05:00
62792ddaed
adrv9371x: Change the axi_adxcvr cores addresses
...
Because the S_AXI interface of the axi_adxcvr core was infered
using the process adi_ip_properties, the interface address range
has changed from 4k to 64k. As a result, all the addresses of
the axi_adxcvr cores were changed and realigned.
2017-01-19 15:23:03 +02:00
ecd152c90d
pzsdr1: ccbrk_cmos, fix clkdiv parameters
2017-01-18 12:04:04 +02:00
165ba76d9d
pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2
2017-01-18 12:01:24 +02:00
319a883c00
pzsdr2: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-18 12:00:10 +02:00
9344dd34dc
zcu102: Update project to include clkdiv
2017-01-16 14:47:31 +02:00
4dcad7e116
fmcomms2: zcu102, update clkdiv device parameter
2017-01-16 14:38:37 +02:00
b622b6592e
FMCOMMS5/ZCU102 : Merge from njpillitteri/hdl:dev
...
Pull request Dev #26
2017-01-13 14:47:16 +02:00
d2e7b6b635
fmcomms5: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-13 14:18:59 +02:00
a36057679a
fmcomms2: Update Makefiles
2017-01-13 14:16:21 +02:00
15c5bc7012
fmcomms2: zcu102, changed clkdiv C_SIM_DEVICE parameter to ultrascale
2017-01-13 13:57:32 +02:00
b84325d43f
fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection
2017-01-13 13:56:04 +02:00
f003b5b35a
fmcjesdadc1: Reduce SYSREF period
2017-01-12 16:10:45 +02:00
e77428c50e
fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4
...
- removed ILA
2017-01-11 18:12:35 +02:00
37d54bb984
fmcjesdadc1/a5gt- max delay fit only
2017-01-04 16:04:19 -05:00
8b74e911b8
fmcjesdadc1/a5gt- qr to ddio max delay
2017-01-04 14:10:44 -05:00
e4e5b30ade
fmcadc5: Integrate ad_sysref_gen into the project
2017-01-03 13:52:39 +02:00
14ded4f123
fmcjeadadc1/a5soc- ad_sysref_gen updates
2016-12-22 15:59:45 -05:00
b089173b4c
fmcjesdadc1/a5soc- cpu clock is 50m for a5gt also
2016-12-22 14:14:21 -05:00
aa6c94c993
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
18660c7ab4
fmcjesdadc1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
2bea337aa2
fmcjesdadc1/a5gt- use 50m-mem-cpu-clk
2016-12-22 14:14:21 -05:00
5d683943ab
fmcjesdadc1/a5gt- remove ad-sysref-gen-pack
2016-12-22 14:14:21 -05:00
f1168f9e29
fmcjesdadc1/a5gt- use xilinx setup 2-dma
2016-12-22 14:14:21 -05:00
1ceec2e2a9
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
2016-12-22 14:14:21 -05:00
eba30b0cde
projects/altera- qii_auto_pack option
2016-12-22 14:14:21 -05:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
3e57ff1fc5
z-mpsoc- map 0x4-0x8,0x7-0x9
2016-12-20 16:14:38 -05:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
da7f4608a8
fmcjesdadc1/usdrx1: Clean up the mess
...
Delete accidentally commited generated files.
2016-12-19 15:35:20 +00:00
f47863bbcf
usdrx1: Integrate ad_syref_gen into the project
2016-12-19 14:36:01 +00:00
8d799d0316
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
0c42e04bc3
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
67390c2a95
ad6676evb: Update projects with ad_sysref_gen
2016-12-19 10:52:25 +00:00
8879218502
a5gte: Fixed timing violations
2016-12-16 15:37:51 +02:00
c0b0f9b7e9
ad6676evb: Connect SYS_REF to GPIO
2016-12-14 17:55:50 +02:00
557efed5d9
ad6676evb: Update clock constraints
2016-12-14 17:55:49 +02:00
3a2c889115
ad6676evb: Update GT configuration
2016-12-14 17:55:49 +02:00
d962614000
usdrx1/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:23:51 +02:00
d5165ca81f
motcon_fmc: Tie unused pins to GND
2016-12-13 19:20:13 +02:00
1515b6f1af
fmcomms7/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:18:18 +02:00
8846141467
fmcomms1/kc705: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:16:31 +02:00
c455d2d64f
fmcadc2/vc707: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:15:44 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
06aab8ebbd
pzsdr1: Set the device core to 1R1T mode
2016-12-09 16:35:46 +02:00
8e69c838e1
common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
2016-12-09 13:54:39 +02:00
23c91ca48a
pzsdr1/lvds: The interface runs at max 122.88 MHz
2016-12-09 11:45:11 +02:00
f799c40cf0
usdrx1/a5gt- xcvr interface changes
2016-12-08 16:05:23 -05:00
c114888956
usdrx1- updates
2016-12-08 16:05:23 -05:00
b0eff57b0f
fmcomms2/zc702: Fix critical warnings
2016-12-08 19:54:52 +02:00
3dceb53984
fmcadc2/vc707: Fix timing violations
2016-12-08 19:51:18 +02:00
252c67ceff
fmcomms6: Delete project
...
This project will not be supported in further releases.
2016-12-08 17:22:41 +02:00
fb287d0178
kcu105- updates to match xilinx trd
2016-12-08 09:32:33 -05:00
3bc9df4c51
fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core
2016-12-07 21:43:19 +02:00
8eaae98728
fmcadc2: Updates
2016-12-07 21:43:19 +02:00
801da3cb25
daq3/kcu105- fix timing violations
2016-12-06 12:31:40 -05:00
2d7fb03b93
adrv9371x/a10gx- fix os xcvr parameters
2016-12-06 12:31:40 -05:00
ad96c5e881
daq3/zc706: Change the speed grade of the FPGA to 3
2016-12-06 15:24:23 +02:00
8f94103f8b
daq1/a10gx: Makefile fix
2016-12-06 15:24:23 +02:00
95ee7c093c
daq1/a10gx: Update system_bd port names
2016-12-06 15:24:23 +02:00
b7143a7a3b
daq1/a10gx: Update IO pin assignments
2016-12-06 15:24:22 +02:00
a415625069
daq1/a10gx: Add spi wrapper file to the project
2016-12-06 15:24:22 +02:00
e30a80fda0
daq1_spi: Delete device specific macro instantiation
2016-12-06 15:24:21 +02:00
7a8dc92b84
usb_fx3: Add interrupt monitor and increase ILA data depth
2016-12-06 11:55:28 +02:00
1e4bdea80c
usrpe31x: Fix Makefile
2016-12-06 11:07:42 +02:00
4b7bf422ee
pzsdr2/ccbox- remove imu intr on pl
2016-12-05 10:21:42 -05:00
351811e13f
pzsdrx/ccbox- imu intr on gpio
2016-12-05 10:18:40 -05:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
6e89ac3d65
pzsdr2: ccusb_lvds, add flag_a,flag_b signals
2016-11-30 17:39:02 +02:00
0faa1ebff2
pzsdr1: ccusb_lvds, add flag_a,flag_b signals
2016-11-30 17:38:04 +02:00
84a76b9dea
imageon: Invert HDMI TX clock
...
The ADV7511 samples the parallel data bus at the rising edge of sample
clock. Generate the clock so that the falling edge is aligned to updating
the bus data. This creates larger timing margins on each side of the
sampling edge and makes the design more robust.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 15:43:24 +01:00
24cc8d284b
imageon: Increase RX DMA FIFO size
...
Increase the RX DMA FIFO to be able to better compensate for momentarily
memory bus contention. This has shown to resolve occasional overflows that
would occur under high system memory load.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
99dae73d96
imageon: Connect hdmi_rx_core output clock to DMA
...
Connect the HDMI RX core output clock to the DMA rather than connecting the
HDMI RX input clock directly. This will allow the HDMI RX core to modify
the clock and e.g. insert clock buffers or similar.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
07217740b5
imageon: Increase HDMI RX clock constraint
...
The ADV7611 is rated for a maximum clock rate of 165MHz. Increase the clock rate constraint to match this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
284fbac571
usdrx1: Xcvr updates, so that the channel parameters are correctly configured from boot time
2016-11-28 14:16:07 +02:00
45fd4f806d
fmcjesdadc1: Fixed RX_PMA_CFG parameter
2016-11-25 16:33:58 +02:00
11b57290f1
fmcadc5- replaced with axi_adxcvr
2016-11-23 16:22:05 -05:00
22e230618c
scripts/adi_board.tcl- support multiple xcvrs
2016-11-23 16:22:05 -05:00
862bd7ef2c
daq3/zc706- xcvr changes
2016-11-23 15:02:20 -05:00
4e3e623530
pzsdr2/ccpci- updates
2016-11-23 14:02:59 -05:00
e5d3bae54d
projects/ad6676-adrv9371: xcvr updates
2016-11-23 11:06:22 -05:00
daa3df4b96
projects/- xcvr updates
2016-11-22 16:23:05 -05:00
8f562fd069
xcvr updates- board procedure
2016-11-22 14:43:36 -05:00
b1a9bd96f1
daq2: xcvr pll changes
2016-11-22 12:53:29 -05:00
750b23621b
board-tcl: xcvr qpll/cpll changes
2016-11-22 12:53:02 -05:00
4ed7469286
fmcadc4/zc706- updates
2016-11-22 10:32:05 -05:00
8c4279f618
pzsdr1: Added ccusb_lvds initial project
2016-11-22 16:58:34 +02:00
3d0049d274
pzsdr2: ccusb_lvdsr, updated project for the latest schematic
2016-11-22 16:55:52 +02:00
aff45eae5f
fmcadc2: xcvr updates
2016-11-21 18:45:38 +02:00
69ee410d3d
fmcomms2/zc706pr- bypass pr as default
2016-11-21 09:45:10 -05:00
4739d05269
zc706pr/common- removed
2016-11-18 14:52:39 -05:00
f43248c2bc
common/pzsdr*- removed
2016-11-18 11:32:43 -05:00
0d75bcb606
pzsdr2: ccbox: Use DMA interface 0+1 for audio
...
There is a bug in the ps7 component specification that causes critical
warnings to appear in the build log if DMA interface 0 is disabled, but any
other DMA interface is enabled.
Work around this issue by using DMA interface 0 and 1 instead of 1 and 2
for the I2S DMA.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 14:03:46 +01:00
b62f60b0da
pzsdr1/ccbox- updates
2016-11-17 16:14:28 -05:00
935f8a5c7b
pzsdr1/ccbox- constraints
2016-11-17 16:13:53 -05:00
4f65bcb3b2
pzsdr1/ccbrk_cmos- updates
2016-11-17 15:32:49 -05:00
e85dd2740a
pzsdr1/ccbrk_lvds- updates
2016-11-17 15:32:25 -05:00
a61da1d2ac
pzsdr1/common- updates
2016-11-17 15:31:25 -05:00
aa02ca875f
pzsdr1- common files
2016-11-17 13:40:25 -05:00
8c25402d53
pzsdr1- common files
2016-11-17 13:40:04 -05:00
4dae754287
pzsdr1- added readme
2016-11-17 11:29:01 -05:00
778638a7a1
pzsdr2- make updates
2016-11-17 10:26:45 -05:00
74bf4dfb80
pzsdr2- gpio- turn-around
2016-11-17 10:24:50 -05:00
d0166a4c7e
ccbox- updates
2016-11-17 10:24:11 -05:00
c2b7cbd61b
ccbox- constraints
2016-11-17 10:23:51 -05:00
5e6b931150
ccbox- added
2016-11-17 09:28:33 -05:00
fb5d36b250
pzsdr2- update ccfmc
2016-11-16 16:27:41 -05:00
95c44b687e
pzsdr2- fmc/pci constraints
2016-11-16 16:27:41 -05:00
11347c49be
fmcomms11- device set to -3
2016-11-16 13:43:07 -05:00
b85a282748
fmcomms11- lane swap
2016-11-16 10:26:47 -05:00
bdd14c3874
README: Delete second rule under headers
...
By default there is a rule under each header, no need for another one.
2016-11-16 11:04:43 +02:00
81e47edcd5
README: Set links for documentation
2016-11-16 10:57:39 +02:00
fabbe4981e
Update README.md
...
updated
2016-11-15 16:15:55 -05:00
538a1c977f
pzsdr2: make files
2016-11-15 16:00:55 -05:00
4905e80df8
Update README.md
...
updated
2016-11-15 14:16:46 -05:00
db243df97e
pzsdr2- updates
2016-11-15 14:16:06 -05:00
0897716167
fmcadc4: xcvr updates
2016-11-15 16:03:52 +02:00
cac4057449
daq2/common: Altera updates
2016-11-15 16:03:52 +02:00
cfd3ea61f1
pzsdr-to-pzsdr2
2016-11-14 14:12:22 -05:00
f64b44c8ac
sdrstk2pluto- contents
2016-11-11 13:52:57 -05:00
2ececad58c
sdrstk-2-pluto
2016-11-11 13:49:04 -05:00
c80033cb1b
util_fir_int: removed s_axis_data_tvalid and updated sdrstk
2016-11-11 17:52:19 +02:00
e62fe0c086
fmcjesdadc1- a5gt/a5soc- sysclk is different
2016-11-11 10:34:18 -05:00
7008c641b5
axi_adrv9371/zc706: Constraints update
...
From source *jesd_rstgen* is a false path for TX and RX_OS too.
2016-11-11 10:35:09 +02:00
85eac8c811
fmcjesdadc1/a5*- updates
2016-11-10 16:57:06 -05:00
959055bd54
common/a5gt- updates
2016-11-10 16:56:35 -05:00
7a2c713a4e
fmcjesdadc1/a5* - hdlmake.pl
2016-11-10 11:37:06 -05:00
c6730ab2d7
fmcjesdadc1/a5gt- updates
2016-11-10 11:36:41 -05:00
c207589f4b
fmcjesdadc1/a5gt - qsys2tcl flow
2016-11-10 11:32:29 -05:00
8af0731bb0
a5gt- qsys2tcl flow
2016-11-10 11:30:18 -05:00
7a606cbae1
sdrstk: Maximum clock frequency is 61.44 in CMOS mode
2016-11-10 17:45:35 +02:00
d29ef14f36
sdrstk: Configured ad9361 in 1r1t mode
2016-11-10 17:06:42 +02:00
a54092c9bb
fmcjesdadc1: Update projects to xcvr framework
...
This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
d6918de19e
ad6676: Update projects to xcvr frame work
2016-11-10 10:39:46 +02:00
3cc416ca60
pzsdr1- fix typo on system_ps7
2016-11-09 12:04:30 -05:00
35c2dd5d6d
adrv9371x/zc706: Fix constraints
2016-11-09 16:34:08 +02:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
aef3e87d7e
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:48 -05:00
53c2f0642b
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:33 -05:00
f0af8216ce
common/a5soc- device can not run at 100M cpu clock
2016-11-08 15:19:23 -05:00
d9cfccc05f
common/a5soc- gpio in/out separation
2016-11-08 15:19:02 -05:00
acb9bf3902
hdlmake- a5soc/a5gt- updates
2016-11-04 15:02:57 -04:00
6b492b79db
a10soc - remove default assignments
2016-11-04 15:01:19 -04:00
8ea9beffaf
fmcjesdadc1- a5soc tcl updates
2016-11-04 15:01:19 -04:00
4e99c3be9a
a5soc- tcl flow updates
2016-11-04 15:01:19 -04:00
ce3b6a2d3f
adrv9371x: Updated constraints for altera projects
2016-11-04 18:20:46 +02:00
0dfbb0af11
arradio/c5soc- constraints changes- interface 1r1t
2016-11-03 11:25:52 -04:00
128ca7719a
ccpci_lvds- rev.d. xcvr pin changes
2016-11-02 16:41:04 -04:00
1cbea90bac
altera - a10gx bank swap
2016-11-01 12:41:25 -04:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
671a547c2b
hdlmake- updates
2016-11-01 12:41:25 -04:00
d010f3e687
sdrstk: Update Makefile to remove pack/cpack dependancy and add util_fir_dec/util_fir_int dependancy
2016-10-28 16:13:52 +03:00
ac8a6124af
sdrstk: Added interpolation and decimation filters. Removed cpack/upack
2016-10-27 19:33:28 +03:00
50552ce7d6
adrv9371x- altera updates
2016-10-27 09:25:00 -04:00
f752f0c9d7
a10soc- xcvr updates
2016-10-27 09:25:00 -04:00
d4c7b7ca57
ccusb_lvds: Fixed IIC constraints
2016-10-26 11:12:02 +03:00
6607aa707d
pzsdr1: Renamed projects to have lvds/cmos sufix
2016-10-26 11:09:43 +03:00
9ff92fdf5b
pzsdr: Renamed projects to have lvds/cmos sufix
2016-10-26 11:07:29 +03:00
b8363d778d
arradio: Makefile update
2016-10-25 20:36:56 +03:00
138eeebc9b
ccusb_lvds: Initial commit
2016-10-25 16:32:44 +03:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
7e57a89ce5
daq1: Add support for A10GX
2016-10-24 11:43:33 +03:00
c9ac870086
usrpe31x- updates
2016-10-21 13:59:43 -04:00
7b958fed87
hdlmake- updates
2016-10-21 13:59:43 -04:00
48e90f0e9b
usrpe31x- added
2016-10-21 13:59:43 -04:00
801f980aeb
adrv9371: Fix parameter name
2016-10-21 12:50:20 +03:00
3abd87631a
fmcomms11: Fix parameter name
2016-10-21 12:49:48 +03:00
7db0c03a92
pzsdr1+ccbox -- updates
2016-10-19 10:32:28 -04:00
c1b7c5e77a
usb_fx3: Added FIFO on the FX3 to Zynq path, between FX3 core and DMA core
2016-10-19 09:30:51 +03:00
17cfdd6be9
fmcomms2/a10gx: Update Makefile and qsys script
2016-10-18 12:42:14 +03:00
918ce45e2a
pzsdr1/ccbox- updates
2016-10-17 16:29:57 -04:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
950acaed15
ccbox- copy
2016-10-17 16:29:57 -04:00
7c541c704a
usdrx1: ZC706, Update project to the new GT framework
2016-10-14 18:08:08 +03:00
1d1fe26624
fmcomms7: ZC706, Update project to new GT framework
2016-10-14 17:32:23 +03:00
5bb77109ca
daq2/a10gx- make fix
2016-10-10 13:03:44 -04:00
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
e5cf417576
daq2/mb- xcvr procedures
2016-10-10 12:51:30 -04:00
273073a584
daq2/kcu105- xcvr procedure
2016-10-10 11:12:47 -04:00
b3d3876dc5
imageon: ZC706, updated system_top to remove part of the Warnings.
...
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:33:42 +03:00
9efc45f0b6
imageon: Zed, updated system_top to remove part of the Warnings.
...
- spi csn signals should be tied to 1 if spi is not used
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:31:25 +03:00
8875c5bef3
fmcomms6: ZC706, updated system_top to remove part of the Warnings
2016-10-10 16:43:23 +03:00
fcd56a2f90
daq3/a10gx: Update project to the new GT framework
...
- Update common script
- Update system_top, some port names were changed
- Update constraint files
2016-10-10 16:22:08 +03:00
94f55f20e9
adv7511: KCU105, updated system_top to remove part of the Warnings
2016-10-10 16:12:17 +03:00
f464497062
cn0363: Microzed, updated system_top to remove part of the Warnings
2016-10-10 16:08:59 +03:00
2e605fc060
cn0363: Zed, update system_top to remove part of the Warnings
2016-10-10 15:56:46 +03:00
a12d34a98b
adv7511: Zed, updated system_top to remove part of the Warnings
2016-10-10 15:54:34 +03:00
c737afebf8
adv7511: KC705, updated system_top to remove part of the Warnings
2016-10-10 13:24:40 +03:00
74faac9210
ad9467_fmc: KC705, updated system_top to remove part of the Warnings
2016-10-10 13:19:55 +03:00
ffaf78665f
daq2- xcvr procedures
2016-10-06 14:44:20 -04:00
3b55822db3
daq2- xcvr connect
2016-10-06 14:09:27 -04:00
721ee98a06
zcu102- misc fixes
2016-10-06 10:18:14 -04:00
8965bcffb7
make: Update make files for DAQ3
2016-10-06 10:27:00 +03:00
9ace02a227
daq3/a10gx: Update project to the new GT framework
2016-10-06 10:25:25 +03:00
58c4abd8af
daq3/kcu105: Update project to the new GT framework
2016-10-06 10:23:52 +03:00
ca4dca87e2
daq2- updates
2016-10-05 14:02:59 -04:00
baabe20766
common/zcu102- spi connections & clock
2016-10-05 14:01:59 -04:00
bab9b2df0b
daq3/zc706: Update project with the new transceiver modules
2016-10-05 17:41:25 +03:00
c196b5bf68
ad6676evb: VC707, fixed system top gpio_bd datawidth
2016-10-05 15:50:43 +03:00
0208335ef3
hdlmake- updates
2016-09-30 13:20:22 -04:00
27c9bdddb6
daq2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
8e1034946f
fmcomms2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
9afff7ae60
common/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
33f9ed33c7
projects- ultrascale+
2016-09-30 11:55:10 -04:00
0ded52d8f6
daq2/zcu102- kcu105 copy
2016-09-30 11:55:10 -04:00
7290bcc81a
hdlmake- updates
2016-09-29 11:50:58 -04:00
4950c6c773
adrv9371x - xcvr updates
2016-09-29 11:50:58 -04:00
4a5b7fc723
scripts- reconnect added
2016-09-29 11:50:58 -04:00
e40311eee9
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
2016-09-29 09:14:37 +01:00
4239f64125
dacfifo- board pin warnings
2016-09-27 14:49:20 -04:00
751a66eb72
plddr3/zc706- board pin warning
2016-09-26 15:20:37 -04:00
79b9e21be8
board- xcvr procedure
2016-09-26 15:20:18 -04:00
8314efd4e9
fmcomms11- xcvr updates
2016-09-26 15:19:29 -04:00
7fd9280cbf
fmcomms11- xcvr updates
2016-09-26 15:19:05 -04:00
f5809b8817
adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port
2016-09-24 10:09:05 +03:00
2d307d5f58
a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design
2016-09-24 10:06:35 +03:00
df37a23a48
pzsdr/ccfmc- rgmii critical warnings fix
2016-09-22 11:38:43 -04:00
dc6f7bbc4e
pzsdr/ccfmc - loopback updates
2016-09-22 11:18:13 -04:00
0e2572bbd8
pzsdr- ccbrk_cmos- loopback changes
2016-09-21 13:16:04 -04:00
14ad1ea741
pzsdr- swap clear-up
2016-09-21 13:15:40 -04:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
143423e3b9
adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera
2016-09-21 18:13:02 +03:00
500d8bfb90
adrv9371x: A10GX, fix makefile and system_qsys.tcl script
2016-09-21 18:11:35 +03:00
79f34c9de7
ccbrk- test updates
2016-09-21 11:04:22 -04:00
a2e60cf693
ccbrk - test
2016-09-21 11:04:22 -04:00
3ca9fe0919
sdrstk- remove critical warnings from ps7
2016-09-16 14:06:12 -04:00
f1e787f86b
fmcomms2: TDD control is enabled by default
2016-09-16 14:45:39 +03:00
2a7bc31c01
pzsdr1- disable gpreg constraints
2016-09-15 13:49:04 -04:00
67d4e71ff0
pzsdr1- disable gpreg constraints
2016-09-15 12:41:40 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
631923e9f0
usb_fx3: Update to Vivado 2016.2
2016-09-14 15:41:27 +03:00
9118ca3986
version_upgrade: Update MOTCON2 to 2016.2
2016-09-14 10:58:06 +03:00
cf9ac730a8
pzsdr1- new rev. board delays
2016-09-13 10:32:13 -04:00
9a2d2e8a02
version_upgrade: Update FMCADC4 to 2016.2
2016-09-13 15:04:11 +03:00
236a938425
daq2/a10gx- qsys updates
2016-09-12 14:57:50 -04:00
5df30ac6b0
daq2/a10gx- xcvr sharing
2016-09-12 14:57:50 -04:00
521c41ce32
adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
2016-09-08 11:44:45 +03:00
40c9fc92c1
a10soc: Switched to tcl flow
2016-09-08 11:31:06 +03:00
0d095f5da9
a10gx: Added system_type variable in common design
2016-09-08 11:29:14 +03:00
bae63ae5b1
version_upgrade: Update the DAQ3 project to 2016.2
2016-09-06 11:41:37 +03:00
b8c34791d5
version_upgrade: fmcjesdadc1 updated to 2016.2
...
Xilinx IP core JESD204 is updated to version 7.0
2016-09-06 11:41:37 +03:00
b837883b98
pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection
2016-09-01 17:16:59 +03:00
93fa5aeec3
fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
2016-09-01 16:11:39 +03:00
dc21384002
pzsdr: Update ccpci base design
2016-09-01 09:06:30 +03:00
2f9ac4a342
altera- qsys-script does not support most tcl commands
2016-08-30 11:50:36 -04:00
917da79da1
altera- source defaults for qsys-script
2016-08-30 11:50:36 -04:00
8192e755e1
altera- defaults
2016-08-30 11:50:36 -04:00
1eccf5af07
fmcomms7: Update common design to Vivado 2016.2
2016-08-30 16:46:15 +03:00
2015bcedaa
fmcadc2: Update common design to Vivado 2016.2
2016-08-30 16:42:58 +03:00
6f0d124861
fmcadc5: Update to Vivado 2016.2
2016-08-30 16:09:28 +03:00
4248b9373a
ad6676evb: Update to Vivado 2016.2
2016-08-30 16:08:07 +03:00
a6e6b3f96e
version_upgrade: Update fmcomms1 common design to Vivado 2016.2
2016-08-29 15:59:15 +03:00
2e59f377e1
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
2016-08-29 09:50:46 +03:00
271029768c
pzsdr/cmos - swap==1
2016-08-26 10:31:00 -04:00
d18f6aa816
adrv9371x: A10GX, added adcfifo
...
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
5cc2ab37a5
version_upgrade: Common ZC702 get an upgrade to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 10:20:04 +03:00
cd0c981b50
projects/scripts: Fix to prevent a warning
...
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
2016-08-26 10:08:00 +03:00
6ab137a0e9
projects/scripts: Cosmetics
2016-08-26 10:07:08 +03:00
9dfcfe6146
version_upgrade: adv7511 common script to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 09:52:01 +03:00
264bde77ad
sdrstk- SWAP==1 option
2016-08-24 12:07:13 -04:00
3c6cfdc7b5
adrv9371x: A10GX, switched TX lanes
2016-08-24 18:06:14 +03:00
215edb11c6
adrv9371: A10GX, updated design
...
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
320f87d63b
sdrstk- fix spi/port connections
2016-08-22 16:52:43 -04:00
270f8a6bbe
adrv9371x: Updated project common
2016-08-22 16:58:21 +03:00
f1b834ab25
scripts: Update script so that all interconnects are optimized for performance
2016-08-22 16:56:02 +03:00
c6b065c349
zc706: Updated DDR3 dacfifo
2016-08-22 16:48:52 +03:00
f697490de6
hdlmake- updates
2016-08-19 15:59:41 -04:00
5c35012f54
sdrstk- updates
2016-08-19 15:59:13 -04:00
8582517712
sdrstk- updates
2016-08-19 15:56:48 -04:00
67bf8f8e78
scripts- fix path and device defaults and override
2016-08-19 15:56:07 -04:00
6ef9555909
sdrstk- added
2016-08-19 13:45:40 -04:00
41203d07e9
adrv9371x: A10GX, update SPI connection
2016-08-18 17:42:27 +03:00
03c83b59bf
adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm
2016-08-17 19:03:53 +03:00
5d0e08d92e
common/vc707- 2016.2 version
2016-08-17 10:36:19 -04:00
73413366bc
daq2/all - warnings fix
2016-08-17 10:36:00 -04:00
0b6fbf2208
daq2/vc707- 2016.2 updates
2016-08-17 10:34:06 -04:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
0694a5015d
kc705- 2016.2 version
2016-08-16 12:54:39 -04:00
8311098384
daq2/kc705- adxcvr changes
2016-08-16 12:54:39 -04:00
8464816c82
dmafifo-split to adc/dac
2016-08-16 12:54:39 -04:00
eb55f600fb
adrv9371x: Initial commit
...
-need to fix dc filter module for AD9371 / altera
2016-08-16 15:50:46 +03:00
5c27ccd1fa
adrv9371x: Added common qsys tcl
2016-08-16 15:34:10 +03:00
4658686ae1
adrv9371x/a10soc: Misc changes for being able to run Linux
2016-08-16 11:56:25 +03:00
39c1c83d00
adrv9371x/a10soc: Fix spi_csn assignment
2016-08-12 10:07:11 +03:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
5d93e542ed
daq2-kcu105: 2016.2 updates
2016-08-11 10:00:41 -04:00
16ad0f4379
kcu105- 2016.2 update
2016-08-11 10:00:41 -04:00
285059aed0
kcu105: Don't use phy reset automation, as it's not supported for KCU105
2016-08-09 10:19:57 +03:00
452d4706d3
kcu105: Update base project to 2015.4.2
...
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
c6f4def93d
altera- make mmu a make switch
2016-08-08 11:54:51 -04:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
f784557895
lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera
2016-08-08 15:06:34 +03:00
8f61e11a70
pzsdr: ccpci: Add PCIe reset monitor
...
For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.
Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
91782989ad
pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13
...
The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
AndreiGrozav
Nick Pillitteri
Dragos Bogdan
István Csomortáni