5 Commits (62eb5a067d28700c6f07aa9664bf6965526748bf)

Author	SHA1	Message	Date
Istvan Csomortani	e856a99e49	adi_jesd204: add_instance command must have a version attribute	2020-08-11 10:14:18 +03:00
cycollineau	b93c1e6e90	intel/adi_jesd204: add bonded clock network support (#408) ... * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>	2020-01-09 17:45:32 +02:00
Istvan Csomortani	aeaefd2c1c	intel/jesd204_phy: Add support for external coreclkin ... In Subclass 1 mode an external device clock (core clock) is used, instead of the PCS output clock, to drive the link and transport layer. Define an additional parameter, which can be used to enable clock input port for the PHY module, which can be used as rx|tx_coreclkin source.	2019-10-02 15:32:17 +03:00
Istvan Csomortani	5329458a62	library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl	2019-06-29 06:53:51 +03:00
Istvan Csomortani	79b6ba29ce	all: Rename altera to intel	2019-06-29 06:53:51 +03:00