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252 Commits (61be003017ef020d092a3b57eaf864d32cefbbb8)

Author SHA1 Message Date
Istvan Csomortani e361bbbd04 Revert "fmcomms2_udc: Initial check in" 
This reverts commit ddc7c845e9.
 2014-10-10 14:48:55 +03:00
Paul Cercueil 7659f3438c AD9467: Fixup swapped net names 
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
 2014-10-10 12:33:07 +03:00
Rejeesh Kutty adf4893a27 usdrx1: remove constraints and other changes 2014-10-09 15:25:08 -04:00
Istvan Csomortani ddc7c845e9 fmcomms2_udc: Initial check in 
FMCOMMS2 with an additional SPI port for the up/down converter board
 2014-10-09 19:01:22 +03:00
Istvan Csomortani 6f77af4aff fmcjesdadc1: Upgrade project to 2014.2 2014-10-09 18:55:27 +03:00
Istvan Csomortani 2da395926e fmcomms2: Upgrade project to 2014.2 2014-10-09 18:54:33 +03:00
Istvan Csomortani 4f6aa159b8 mitx045: Base design now support 2014.2 2014-10-09 15:11:28 +03:00
Adrian Costina edeeafa47d ad9671_fmc: Added sof information to the AD9671 driver 2014-10-09 14:52:25 +03:00
Istvan Csomortani 072e11c661 ad9467_fmc: Upgrade the axi_quad_spi core 2014-10-08 15:22:58 +03:00
Istvan Csomortani fc38249150 ad9467 ZED: Fix over range signal path, and the dma interface. 2014-10-08 11:24:44 +03:00
Istvan Csomortani 15db557bd6 ad9467 ZED: Cosmetic changes on bd script. 2014-10-08 11:24:32 +03:00
Istvan Csomortani 82717b354a ad9467_fmc : Upgrade project to 2014.2 2014-10-08 11:21:43 +03:00
Istvan Csomortani b2d0260130 ad9467_fmc: Prevent to use concatenation module on SPI interface 
This module cause unnecessary issues during version upgrades.
 2014-10-08 11:20:45 +03:00
Rejeesh Kutty 27153fff41 ad9625x2_fmc: updated to 2014.2 2014-10-07 16:05:09 -04:00
Adrian Costina 2dfcb0c599 usdrx1: Initial commit for a5gt 
axi_ad9671: added start of frame information to the altera core.
 2014-10-07 19:41:54 +03:00
Istvan Csomortani 95842b8949 ad9434_fmc: Fix adc_valid signal path 2014-10-07 18:02:33 +03:00
Istvan Csomortani 115f33b8d6 ad9434_fmc: Fix pin constraints for ZC706 2014-10-07 17:58:29 +03:00
Istvan Csomortani c1213ffe71 ad9434_fmc: Fix SPI interface 2014-10-07 17:51:14 +03:00
Michael Hennerich cd42345324 projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-10-07 09:17:24 +02:00
Rejeesh Kutty bca8ec0160 daq2: 2014.2 and ver.d 2014-10-06 14:56:01 -04:00
Rejeesh Kutty c375b5b26e daq3: vivado build 2014-10-06 10:34:02 -04:00
Rejeesh Kutty 525373fc04 daq3: daq2 copy 2014-10-06 10:34:00 -04:00
Rejeesh Kutty 210da4116f scripts: initial commit 2014-10-03 16:13:34 -04:00
Rejeesh Kutty f0927afd0b ad9625_fmc: add dma fifo for non-zynq 2014-10-01 14:51:14 -04:00
Adrian Costina 89964be59e fmcomms1: Updated project to vivado 2014.2 2014-09-30 10:32:18 +03:00
Adrian Costina 041d8faaf7 common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2 2014-09-30 10:31:00 +03:00
Rejeesh Kutty 922bc6f03a fmcadc3: 16bit - but ignored 4 lsb(s) 2014-09-29 15:26:30 -04:00
Adrian Costina 3c25c1171d fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms 2014-09-26 10:28:07 -04:00
Istvan Csomortani 87c4c73e22 ad9434: Fix adc_clk constraint 
ADC clock is 500 Mhz.
 2014-09-25 16:54:06 +03:00
Istvan Csomortani 82ed885b53 ad9434: Fix SPI line physical constraints 
SPI lines are not differential.
 2014-09-25 16:53:16 +03:00
Istvan Csomortani ccb0b135ca ad9434: Fix the adc to dma interface. 
All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
 2014-09-25 16:50:09 +03:00
Istvan Csomortani 683561b67d AD9434: Initial check in of the library and project with ZC706 2014-09-24 18:27:17 +03:00
Adrian Costina 1d4bc47cea ad9265: Initial commit 2014-09-23 22:51:42 -04:00
acostina 296983707b usdrx1: Updated project to 2014.2 2014-09-23 22:45:50 -04:00
acostina 5af2474d51 usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization 2014-09-23 22:44:33 -04:00
Adrian Costina bdf01738a1 ultrasound: disconnected ADN4670 chips from SPI lines. 
Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
 2014-09-23 22:30:42 -04:00
Adrian Costina 7e40f99fe9 fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems 2014-09-23 22:28:27 -04:00
Rejeesh Kutty 577441bd0c daq1: clean up dma interfaces 2014-09-23 14:23:41 -04:00
Rejeesh Kutty 7c98a783c5 2014.2 updates 2014-09-23 12:32:33 -04:00
Rejeesh Kutty 1682d9da10 fmcadc3: initial updates 2014-09-22 11:27:17 -04:00
Rejeesh Kutty 5e3076d770 fmcadc3: daq2 copy 2014-09-22 11:27:16 -04:00
Istvan Csomortani dd7bac41c1 daq1 : Update project to 2014.2 
- Cores are upadted
  - Concat module does not swap output anymore
  - Clock signal name ps7_clk_* changed to clk_fpga_*
 2014-09-22 17:33:50 +03:00
Istvan Csomortani f2cd7626f5 adi_project : ZC706 board name changed on 2014.2 2014-09-22 17:33:49 +03:00
Rejeesh Kutty fb5d212370 daq2/kcu105: fixed timing violations 2014-09-19 15:55:42 -04:00
Istvan Csomortani 751bdd6cfc daq1: Update the constraint file 
- tx_ref_clk and rx_sysref need to be differential
  - cosmetic changes
 2014-09-19 18:22:57 +03:00
Adrian Costina f43b5d707e fmcomms2: Reduced clock frequency for ILA to meet timing for ZED 
Modified ZED constraints to 250 MHz for the clock from AD9361
 2014-09-16 16:08:28 -04:00
Adrian Costina d33fb07587 usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32. 
GPIOs for which the directions is known, have been specifically assigned.

The SPI clock has been changed to a lower frequency.
 2014-09-16 15:56:19 -04:00
Adrian Costina d4db53c3b0 usdrx1_spi: Modified module to be compatible with altera 2014-09-16 15:53:11 -04:00
Michael Hennerich a3dbd5ac00 projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-09-16 14:59:36 +02:00
Istvan Csomortani a91f4bb6b9 daq1: General updates 
- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
 2014-09-13 00:23:11 +03:00