0c0617d49e
libraries: Update modules according to guideline
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* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
d9ec44657f
libraries: Correct module name according to the filename
2022-04-01 16:02:46 +03:00
c1721e18dd
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-24 16:29:49 +02:00
4c7be950d1
ad_ip_jesd204_tpl_adc: Fix latency of valid signal
2022-02-16 10:27:50 +02:00
f245448976
ad_ip_jesd204_tpl_ : Add missing dependency
2022-02-07 19:14:01 +02:00
b5092662d5
ad_ip_jesd204_tpl_adc: Refactor external sync
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- Add EXT_SYNC option
- Gate valid while in reset
2022-02-07 19:14:01 +02:00
4e644e4e74
jesd204/ad_ip_jesd204_tpl_dac: External sync refactor
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- Expose EXT_SYNC parameter to sw
- Add external manual sync request
- Add rst to interface
2022-02-07 19:14:01 +02:00
9d8097389c
library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register
2022-01-12 13:43:20 +02:00
080925e8fe
library/jesd204: tpl timing bug fix
2022-01-12 10:14:55 +02:00
8e0a45dea9
jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4
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Current implementation is correct only for datapath width of 8.
The buswidth of latency measurement inside a beat has a fixed width (3 bits)
for each lane that must be taken in account when computing the total latency.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-19 18:14:43 +02:00
7e5a638386
jesd204_versal_gt_adapter_rx/tx: Infer Versal GT interface
2021-11-19 14:01:48 +02:00
cb8cf4b3d2
jesd204/scripts: Helper procedure for TPL width calculation
2021-11-10 14:03:34 +02:00
a381fe3e92
ad_ip_jesd204_tpl_adc: Add value of 14 to CONVERTER_RESOLUTION parameter
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Added new allowed value of 14 for the CONVERTER_RESOLUTION parameter.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-04 12:18:06 +02:00
70cc53bbc8
ad_ip_jesd204_tpl_dac: Move external dac sync bit
2021-10-27 18:36:47 +03:00
076e81a17c
library: Add link to wiki for IPs
2021-10-25 10:44:53 +03:00
dbd5ffe4ed
jesd204_rx: fixed makefile
2021-10-07 12:48:08 +03:00
0c6c28ed84
jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes
2021-10-06 15:49:56 +03:00
51b643b978
Makefile: Fix misc makefiles from projects and library
2021-10-05 14:24:48 +03:00
22e1366bfc
jesd204/jesd204_rx: Define tie off values for unused ports
2021-10-05 14:09:51 +03:00
aa93c17cdc
jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation
2021-10-05 14:09:51 +03:00
1a9e7dbeb4
jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP
2021-10-05 14:09:51 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
12a3f8799e
JESD204 Interface Framework : add logo
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Add a small logo for branding purposes.
Signed-off-by: Robin Getz <robin.getz@analog.com>
2021-09-16 16:49:52 +03:00
8afc03abab
jesd204/ad_ip_jesd204_tpl_dac: Intel: Add support for AD916x preset files
2021-08-16 07:22:50 +03:00
569257c4f3
Fix width of device_cfg_octets_per_multiframe
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The width of the parameter `device_cfg_octets_per_multiframe` doesn't match the width in the submodules and corresponding slave module jesd204_tx, resulting in a warning generated during validation in Vivado. This patch increases the width of this parameter in axi_jesd204_tx.
2021-07-27 11:34:34 +03:00
20fc00a811
jesd204/ad_ip_jesd204_tpl_dac: Support for F=64
2021-07-27 11:31:19 +03:00
c39b6b2ac8
jesd20r_rx/jesd204_tx: Support for F=64
2021-07-27 11:31:19 +03:00
4407d72d42
esd204/ad_ip_jesd204_tpl_adc: Support more datapath widths
2021-07-27 11:31:19 +03:00
c808d8c3c7
ad_ip_jesd204_tpl_adc: Max number of lanes is 32
2021-07-27 10:28:48 +03:00
f0027faf88
adi_jesd204: Add support of 16 lanes
2021-07-27 10:28:48 +03:00
30b491fff7
tb: jesd204: update and automate frame_align_tb
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Fix jesd204 frame_aligh_tb by adding a fifo to solve rx and tx delay.
It saves the data from tx and compares it with the recieved ones from
rx.
2021-07-12 10:30:49 +01:00
54c65013aa
Fix registers mismatches in regmap_tb from jesd 204 rx/tx and dmac
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* dmac_tb: Fix regmap_tb registers mismatches
* jesd204: Fix jes204 rx and tx regmap_tb Octets per multiframe mismatch
2021-05-31 16:47:12 +03:00
60612720cd
jesd204/jesd204_common/sync_header_align: Initial version
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This module creates sync header alignment described in section 7.6.1 of
the JESD 204C specification.
The alignment relies on the bitslip capability of the connected
transceiver.
2021-05-14 15:39:40 +03:00
0c0c6843e3
jesd204/axi_jesd204: Complete clock definitions in out of context mode
2021-05-14 15:39:40 +03:00
e08ca2fc20
jesd204: Add out of context constraint file for link layer cores
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For the out of context flow it is important to have all clocks defined
at the interface, especially if the clock are used in the other constraints.
2021-05-14 15:39:40 +03:00
37238916df
Testbenches: Unify and optimize HDL testbenches
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Create a common 'run_tb.sh' script to be called by every testbench.
Unify file and testbenches names.
Fix util_pack/cpack_tb.
Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui)
Add ascript for that generates output in xml format (used by CI tools).
2021-05-07 19:53:14 +03:00
9413afa41c
jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg
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get_cell on i_lmfc/cdc_sync_stage1_reg doesn't return anything because design was updated.
This generates a CRITICAL WARNING and since the constraint it not necessary anymore, it can be deleted.
2021-03-22 10:55:00 +02:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
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adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
e2a111d74b
jesd204/ad_ip_jesd204_tpl_dac: Drop LSBs from wider bus to be compatible with previous implementations
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Add selectable synthesis option for dropping LSBs or MSBs
2021-03-08 10:46:52 +02:00
69bb9df515
jesd204_rx: Set ASYNC_REG attribute for double syncs
2021-03-08 10:46:52 +02:00
8d388dd4f2
jesd204_rx:jesd204_rx_ctrl_64b: Improve timing closure
2021-03-08 10:46:52 +02:00
c2f703f56b
jesd204/jesd204_rx: Make output pipeline stages opt in feature
2021-03-08 10:46:52 +02:00
fd714c181a
jesd204/ad_ip_jesd204_tpl_adc: Make frame alignment opt-in feature
2021-03-08 10:46:52 +02:00
0db7519c18
jesd204_tx:64b: Remove reset
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Remove synchronous reset from datapath to reduce fanout on reset and
help timing closure.
2021-03-08 10:46:52 +02:00
2545e53b0b
jesd204_rx:64b: Remove reset
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Remove synchronous reset from datapath to reduce fanout on reset and
help timing closure.
2021-03-08 10:46:52 +02:00
7b4fa390db
ad_ip_jesd204_tpl_dac: fix capability reg
2021-03-08 10:46:52 +02:00
bfd4c77284
jesd204/jesd204_tx: Expose character replacement capability
2021-02-26 14:41:49 +02:00
5678e72653
jesd204: Increase Rx version to 1.07.a
2021-02-05 15:24:15 +02:00
6f608b6199
jesd204: Increase Tx version to 1.06.a
2021-02-05 15:24:15 +02:00
dd58759cd8
jesd204: Intel: NP12 support
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Dual clock mode is introduced in link layer to support different
datapath widths on the transport layer than on physical layer.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- Device clock : Link clock * input data path width / output datapath width
Supports four clock configurations, single or dual clock mode with or
without external device clock.
The configuration interface reflects the dual clock domain.
2021-02-05 15:24:15 +02:00
Iulia Moldovan
Nick Pillitteri
Laszlo Nagy
Filip Gherman
Dan Hotoleanu
LIacob106
Adrian Costina
Robin Getz
Isaac T
Istvan Csomortani
Alin-Tudor Sferle
stefan.raus