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145 Commits (5f21f5446369e914930599ea593a2df662eef483)

Author SHA1 Message Date
Rejeesh Kutty 5f21f54463 fmcjesdadc1: zc706 version 2014-08-25 14:28:57 -04:00
Rejeesh Kutty fe1eaefcff fmcomms1: zc706 2014-08-22 09:08:55 -04:00
Rejeesh Kutty 280260e54c c5soc: dmac separated slave and master id widths 2014-08-22 09:08:54 -04:00
Rejeesh Kutty b481df0b5f library: local constraints async groups 2014-08-14 15:09:51 -04:00
Rejeesh Kutty 01963b01fc jesd_gt: local constraints 2014-08-14 15:09:49 -04:00
Rejeesh Kutty 9438e2a9e0 spdif: constraints file added 2014-08-14 15:09:48 -04:00
Rejeesh Kutty 1396a215e5 library: local constraints 2014-08-14 15:09:47 -04:00
Rejeesh Kutty 39bb7ca231 a5soc: fmcjesdadc1+hdmi version 2014-08-14 09:05:38 -04:00
Istvan Csomortani 2b15c7313e ad_dcfilter: Fix filter loopback 2014-08-12 14:42:10 +03:00
Rejeesh Kutty a5e3a07375 dma: altera fix id assignments 2014-08-11 16:46:36 -04:00
Istvan Csomortani 9dfbf4a9a6 prcfg: Update the prcfg logic to the new ad9361 interface 2014-08-05 17:54:37 +03:00
Rejeesh Kutty 08a12aaf23 library: register map updates on 9467, 9643 and 9671 2014-07-31 15:19:45 -04:00
Rejeesh Kutty dfd11cb809 ad9467: register map changes 2014-07-30 15:31:09 -04:00
Rejeesh Kutty c215eab696 ad9122: register map updates 2014-07-30 11:32:15 -04:00
Rejeesh Kutty b97bdcdc23 ad9122: register map updates 2014-07-30 11:32:13 -04:00
Adrian Costina a2b728b91e util_adc_pack: added extra registers to meet timing. 
Util_dac_unpack: fixed issue regarding changing from 1 channel to 2
 2014-07-25 17:41:47 +03:00
Adrian Costina 26a019ae6e util_adc_pack: Fixed issue regarding changing from 1 channel to 2 2014-07-25 10:20:49 +03:00
Rejeesh Kutty 59759a8ab3 c5soc: working hdl version 2014-07-24 20:51:41 -04:00
Rejeesh Kutty 6346017763 c5soc: changed to alt_lvds - 250M is too high for cyclone v 2014-07-24 20:51:40 -04:00
Adrian Costina 7000897031 fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack 
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
 2014-07-24 19:57:22 +03:00
Rejeesh Kutty 701dc96016 up_dac_channel: make iq cor coeff(s) tc 2014-07-24 10:10:24 -04:00
Istvan Csomortani 191f994e79 prcfg: Fixed the PRBS lock issue on BIST 2014-07-24 09:41:13 +03:00
Istvan Csomortani db1c931736 ad9625_plddr: PL DDR3 fixes 
- Modified the axi slave interface handler
  - Increased the rfifo_mem input depth to prevent overflow
 2014-07-23 19:34:44 +03:00
Istvan Csomortani 4da8100fe5 ad9625_plddr: Delete trailing whitespaces. 2014-07-23 19:31:07 +03:00
Adrian Costina 54b2cd74bf motor_control: cores modified so they can compile with the new common files 2014-07-23 11:58:50 +03:00
Rejeesh Kutty c0e31aa6c2 daq2: latest hardware 2014-07-21 09:06:57 -04:00
Rejeesh Kutty 2955b9db78 fifo2s: flush if no request, c5soc: 14.0 2014-07-15 16:25:33 -04:00
Rejeesh Kutty e7d5d79e42 daq2/kcu105: gth up and running - as it is commit 2014-07-10 10:56:37 -04:00
Rejeesh Kutty a9992f02b0 fifo2s: bug fixes- on 64mhz dma clock 2014-07-08 16:57:44 -04:00
Rejeesh Kutty b434fe6dd5 fmcomms5: register map changes 2014-07-08 16:57:43 -04:00
Istvan Csomortani dc78ced443 prcfg_lib: Change the prcfg_top interface 
Use the device core's gpio_input and gpio_output registers to get/set
  status and control of PR.
 2014-07-08 12:28:25 +03:00
Istvan Csomortani 75e624ef15 prcfg_lib: Flop the status and mode nets 
Flop the status and mode nets in case of BIST and QPSK configurations.
 2014-07-08 12:23:48 +03:00
Adrian Costina 39ac29bb01 AD9361: Altera, modified address width so that all registers are accessible 
Modified qsys project with the new address span
 2014-07-08 10:41:51 +03:00
Rejeesh Kutty f3b20fd148 axi_ad9625: register map updates 2014-07-03 11:19:31 -04:00
Rejeesh Kutty 1a78ac453e Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel 2014-07-02 15:39:42 -04:00
Rejeesh Kutty a388ccab0a fmcomms2/c5soc: initial checkin 2014-07-02 14:56:00 -04:00
Rejeesh Kutty e4ce00f7fb axi_ad9680: register map changes 2014-07-02 12:50:09 -04:00
Istvan Csomortani 7e5748374d prcfg_lib: Fixed prbs generator for QPSK 2014-07-02 18:14:35 +03:00
Istvan Csomortani 8eb7a55797 prcfg_lib: Fixed the gpio status merge logic 
The previous logic did not passed implementation.
 2014-07-02 18:09:48 +03:00
Istvan Csomortani 9089877c70 prcfg_lib: Fixed the sine tone generator for BIST 2014-07-02 18:00:43 +03:00
Lars-Peter Clausen 8a2b29cdbe axi_damc: Add xfer_req to the FIFO source interface 
The xfer_req signal will be high if DMA core the is expecting data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-07-02 16:05:16 +02:00
Rejeesh Kutty 31abd07613 axi_ad9144: register map changes 2014-07-01 21:43:04 -04:00
Rejeesh Kutty 60dd14bcdb a5soc: removed jtag master control 2014-07-01 12:27:37 -04:00
Rejeesh Kutty b6052773b7 added adc/dac gpio registers 2014-06-27 14:45:58 -04:00
Rejeesh Kutty ba7955c531 fmcomms2: register map modifications 2014-06-26 10:09:03 -04:00
Rejeesh Kutty 4afe6c24e9 Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel 2014-06-25 15:26:21 -04:00
Rejeesh Kutty 10a7804e14 ad9361: altera wrapper updates 2014-06-25 15:26:06 -04:00
Rejeesh Kutty 4fdb3cfc4a ad9250: register map updates 2014-06-25 15:23:57 -04:00
Rejeesh Kutty 4f5d163fcc Merge branch 'master' into devel 2014-06-25 13:07:12 -04:00
Rejeesh Kutty e38813fa9f fifo- monitor status signals 2014-06-25 12:15:13 -04:00