Commit Graph

81 Commits (5f0abc50999a6eb4b740c896fdcacb6b7a7373f5)

Author SHA1 Message Date
Istvan Csomortani 53e07c5d29 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
Laszlo Nagy 70d139af7f jesd204/ad_ip_jesd204_tpl_dac: Fix Intel dependencies
Even if the IQ rotation is disabled in the projects all modules has to be
added to the list of dependencies to avoid compilation errors.
2020-04-08 10:50:28 +03:00
Istvan Csomortani 0f7a3b953a scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
AndreiGrozav 7dcaaea04e library: Update scripts/adi_ad_ip.tcl and IPs
Fix library makefiles dep list using generic vendor info reg

Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
2019-04-09 16:07:14 +03:00
AndreiGrozav 4ae5a6d3d8 library/IPs: Auto-generate bd.tcl Update
Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:

  - axi_ad5766/axi_ad5766_ip.tcl
  - axi_ad6676/axi_ad6676_ip.tcl
  - axi_ad9122/axi_ad9122_ip.tcl
  - axi_ad9144/axi_ad9144_ip.tcl
  - axi_ad9152/axi_ad9152_ip.tcl
  - axi_ad9162/axi_ad9162_ip.tcl
  - axi_ad9250/axi_ad9250_ip.tcl
  - axi_ad9265/axi_ad9265_ip.tcl
  - axi_ad9361/axi_ad9361_ip.tcl
  - axi_ad9371/axi_ad9371_ip.tcl
  - axi_ad9434/axi_ad9434_ip.tcl
  - axi_ad9467/axi_ad9467_ip.tcl
  - axi_ad9625/axi_ad9625_ip.tcl
  - axi_ad9671/axi_ad9671_ip.tcl
  - axi_ad9680/axi_ad9680_ip.tcl
  - axi_ad9684/axi_ad9684_ip.tcl
  - axi_ad9739a/axi_ad9739a_ip.tcl
  - axi_ad9963/axi_ad9963_ip.tcl
  - axi_adrv9009/axi_adrv9009_ip.tcl
  - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
  - axi_hdmi_tx/axi_hdmi_tx_ip.tcl
  - xilinx/axi_adxcvr/Makefile
  - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
  - xilinx/util_adxcvr/Makefile
  - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-30 11:26:11 +02:00
AndreiGrozav ceb08feee2 Add license header on tcl files 2019-03-30 11:26:11 +02:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
Laszlo Nagy ca1ba6a6fe axi_ad9144/axi_ad9152: patch up_tpl_common dependency 2019-02-01 08:28:28 +00:00
Laszlo Nagy 3d7a376f8b Makefile: update makefiles 2018-12-21 17:32:48 +02:00
Laszlo Nagy 8bce4c5b0a jesd204_tpl: update address widths of TPL instances 2018-12-04 14:02:22 +02:00
Lars-Peter Clausen b7ea846c40 ad_ip_jesd204_tpl_dac: Use perfect shuffle helper module
Replace the open-coded instances of a perfect shuffle in the DAC framer with
the new helper module.

Using the helper module gives well defined semantics and hopefully makes
the code easier to understand.

There are no changes in behavior.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-15 15:34:31 +03:00
Lars-Peter Clausen 169f38e7d1 ad_ip_jesd204_tpl_dac: Add support for modes with N or N' != 16
The ad_ip_jesd204_tpl_dac currently only supports JESD204 modes that have
both N and N' set to 16.

Newer DACs like the AD9172 support modes where N and N' are not equal to
16. Add support for these modes.

The width of the internal channel data path is set to N, only processing as
many bits as necessary. At the framer the data is up-sized to N' bits with
tail bits inserted as necessary. This data is then passed to the link
layer.

The width at the DMA interface is kept at 16 bits per sample regardless of
the configuration of either N or N'. This is done to keep the interface
consistent with the existing infrastructure it will connect to like upack
and DMA. The data is expected to the LSB aligned, the unused MSBs will be
ignored.

Same is true for the test-pattern data registers. These register keep their
existing 16-bit layout, but unused MSBs will be ignored by the core.

The PN generators are modified to create only N bits of data per sample.

Note that while the core can now support modes with N' = 12 there is still
the restriction that requires the number of frames per beat to be an even
number. Which means that not all modes with N' = 12 can be supported yet.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-23 18:35:30 +03:00
Lars-Peter Clausen a98bc88b84 ad_ip_jesd204_tpl_dac: Make framer more flexible
The current framer implementation is limited in that it only supports N'=16
and either S=1 or F=1.

Rework the framer implementation to be more flexible and support more
framer setting combinations.

The new framer implementation performs the mapping in two steps. First it
groups samples into frames, as there might be more than one frame per beat.
In the second step the frames are distributed onto the lanes.

Note that this still results in a single input bit being mapped onto a
single output bit and no combinatorial logic is involved. The two step
implementation just makes it (hopefully) easier to follow.

The only restriction that remains is that number of frames per beat must be
integer. This means that F must be either 1, 2 or 4. Supporting partial
frames would result in partial sample sets being consumed at the input,
which is not supported by input pipeline.

The new framer has provisions for handling values for the number of octets
per beat other than 4, but this is not exposed as a configuration option
yet since the link layer can only handle 4 octets per beat. Making the
octets per beat configurable is something for future iterations of the
core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-23 18:35:30 +03:00
Lars-Peter Clausen 870d09d44d axi_ad91{44,52}: hw.tcl: Add missing file
Commit 5d044b9fd3 ("ad_ip_jesd204_tpl_dac: Share PN sequence generator
between all channels") add a new file to the ad_ip_jesd204_tpl_dac, but
neglected to update the hw.tcl for the axi_ad9144 and axi_ad9152 which use
this file.

The result is that Intel project using these cores currently do not build.

Fix it by adding the missing file to the file list.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-23 18:35:30 +03:00
Lars-Peter Clausen 6d362f51ec ad_ip_jesd204_tpl_dac: Drop DAC prefix from parameters
All parameters are DAC related since this is a peripheral that handles
DACs. Having DAC as a prefix on some of the parameter names is a bit
redundant, so remove them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-16 12:10:34 +02:00
AndreiGrozav 8cd88150f1 axi_ad9152: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav 69f3a9c952 axi_ad9152: Update for CORDIC algorithm
Add the new files to the IP list
Propagate DDS parameters to top file
2018-07-18 18:19:30 +03:00
Lars-Peter Clausen d26f929ecc axi_ad9152: Use the generic JESD204 DAC transmitter core
Replace the axi_ad9152 implementation with the new generic JESD204
interface DAC core. The replacement is functionally equivalent.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 17:21:20 +02:00
Lars-Peter Clausen bd251a5fd5 Remove unused DMA overflow signal from DAC DMA interfaces
The DAC DMA will never overflow and unsurprisingly the dac_dovf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 17:21:20 +02:00
Lars-Peter Clausen 2b914d33c1 Move Altera IP core dependency tracking to library Makefiles
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.

For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.

Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.

Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.

This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 35a39ba2e6 Regenerate library Makefiles using the new shared Makefile include
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Adrian Costina 493fc1d48b axi_*: Fix instantiation of up_[adc|dac]_[common|channel]
A couple of new parameters and new ports are missing in several
up_[adc|dac]_[common|channel] instance, and generates warnings. The rule of
thumb is to use full instantiations, defining all the existing parameter and
ports of the module.

Fix all the instantiation of up_[adc|dac]_[common|channel], by defining all its
parameters and ports.
2018-04-11 15:09:54 +03:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen fa9d94bfe8 avl_adxcvr: Perform octet order swap
The ADI transport layer peripherals expect the first octet to be in the
LSBs and the last octet to be in the MSBs. The Altera JESD204 core orders
the octets the other way around though, first octet in the MSBs and last
octet in the LSBS.

Currently this is handled by having each transport layer peripheral swap
the octets around when it is connected to the Altera JESD204 core.

Change this so that rather than having to do the data swizzling in every in
every transport layer peripheral perform it at the input/output of the link
layer peripheral inside the generated block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Lars-Peter Clausen de4fe30238 library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
The external s_axi_{awaddr,araddr} signals that are connect to the core
have their width set according to the specified size of the register map.

If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently
is for many cores) the MSBs of those signals are left unconnected, which
generates a warning.

To avoid this make sure that the signal width matches the declared register
map size.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:25 +02:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Lars-Peter Clausen bd8d676346 library: Use ad_ip_intf_s_axi were applicable
Use the ad_ip_intf_s_axi helper function to create the axi4lite slave
interface for memory mapped peripherals. This slightly reduces the amount
of boilerplate code in the peripheral's *hw.tcl

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:52:37 +02:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 10898d6618 constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
AndreiGrozav 0e1e507541 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
2017-03-30 16:16:02 +03:00
Rejeesh Kutty c8b638e182 ad9152- add prbs generators 2017-01-23 10:31:57 -05:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Rejeesh Kutty 862bd7ef2c daq3/zc706- xcvr changes 2016-11-23 15:02:20 -05:00
AndreiGrozav a505d304af Add up_dac_common missing connections 2016-10-12 13:20:26 +03:00
AndreiGrozav 43ee917d53 Add up_dac_channel missing connections 2016-10-12 13:20:26 +03:00
Istvan Csomortani 15f36af4c2 axi_ad9152: Update core to support Altera platforms 2016-10-10 16:21:49 +03:00
Rejeesh Kutty f6c7aa9005 library- dac parameter changes 2016-09-23 16:15:59 -04:00
Istvan Csomortani 913eafed48 up_drp : Update the DRP interface to support Altera platforms 2016-09-21 15:00:45 +03:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00