Commit Graph

6114 Commits (5edf6c19def5830744a93f116a0a48ebca25235c)

Author SHA1 Message Date
Laszlo Nagy 5edf6c19de adrv9009/zcu102: Hook up ref clock from IBUFDS_GT 2022-02-15 11:09:37 +02:00
Laszlo Nagy 4bd55dc5c2 adrv9009/zc706: Hook up ref clock from IBUFDS_GT 2022-02-15 11:09:37 +02:00
Laszlo Nagy aac4746398 adrv9009/common/adrv9009_bd: Take ref clock from the IBUFDS_GT
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR.  The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :

Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
Laszlo Nagy 3c6c45962a adrv9371x/kcu105: Hook up un-gated ref clock to fabric 2022-02-15 11:09:37 +02:00
Laszlo Nagy 572005abe4 adrv9371x/zcu102: Hook up un-gated ref clock to fabric 2022-02-15 11:09:37 +02:00
Laszlo Nagy 501903bc81 adrv9371x/zc706: Hook up un-gated ref clock to fabric 2022-02-15 11:09:37 +02:00
Laszlo Nagy 39e073e6bf adrv9371x: Use the output of IBUFDS_GTE2 as reference for the clock gens
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR.  The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :

Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
LIacob106 86d754ae85 projects/scripts: Add gtwizard scripts 2022-02-14 10:32:58 +02:00
Adrian Costina 62dc310794 Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF"
This reverts commit a3a610728c.

Quartus doesn't instantiate correctly the buffer
2022-02-09 17:39:29 +02:00
Filip Gherman 4790d334ad dac_fmc_ebz: NUM_LINKS added to system_top.v 2022-02-09 12:23:12 +02:00
Laszlo Nagy 7702079af5 ad_quadmxfe1_ebz: Fix external sync for ADC path 2022-02-08 16:56:01 +02:00
Filip Gherman 3ff2887485 dac_fmc_ebz_vcu118: Initial commit 2022-02-08 14:34:47 +02:00
Filip Gherman 694ebbfbfc dac_fmc_ebz_bd.tcl: Updated bd for multiple tx_ref_clk 2022-02-08 14:34:17 +02:00
Laszlo Nagy 45dae0f3d3 ad9081_fmca_ebz/common: Connect sync at TPL level
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
2022-02-07 19:14:01 +02:00
Laszlo Nagy 8ec657315c adrv9009zu11eg: Drive cpack/upack reset from TPL 2022-02-07 19:14:01 +02:00
Laszlo Nagy d949936a1b adrv9009zu11eg/common: EXT_SYNC updates
- Explicitly enable EXT_SYNC parameter for Rx/Obs
- Loopback manual sync for each TPL  (we do not combine them yet because
  it requires extra CDC logic)
2022-02-07 19:14:01 +02:00
Laszlo Nagy f245448976 ad_ip_jesd204_tpl_ : Add missing dependency 2022-02-07 19:14:01 +02:00
Laszlo Nagy b5092662d5 ad_ip_jesd204_tpl_adc: Refactor external sync
- Add EXT_SYNC option
- Gate valid while in reset
2022-02-07 19:14:01 +02:00
Laszlo Nagy 8c7cca4277 common/up_adc_common: Add ext sync regs 2022-02-07 19:14:01 +02:00
Laszlo Nagy 1b06c74919 common/up_dac_common: Add manual sync request 2022-02-07 19:14:01 +02:00
Laszlo Nagy db49aa652f common/up_dac_common: Add support for explicit disarm control 2022-02-07 19:14:01 +02:00
Laszlo Nagy 4e644e4e74 jesd204/ad_ip_jesd204_tpl_dac: External sync refactor
- Expose EXT_SYNC parameter to sw
- Add external manual sync request
- Add rst to interface
2022-02-07 19:14:01 +02:00
Laszlo Nagy 1ca5abc91e common/up_xfer_cntrl: Fix transfer done timing
up_xfer_done should signalize when a previous control set is
transferred to the other clock domain and the current control set is latched.

If a bit from the up_data_cntrl changes, it should stay in that state until
the up_xfer_done asserts.
2022-02-07 19:14:01 +02:00
sergiu arpadi 63a1233101 ad7134_fmc: Update Readme 2022-02-07 14:41:25 +02:00
sergiu arpadi 4827e5eb18 ad7134_fmc: Switch offload trigger to falling ODR 2022-02-07 14:41:25 +02:00
Sergiu Arpadi 297bed6721 ad7134_fmc: Change ODR signal to output
FPGA is now generating the ODR signal using axi_pwm_gen.
Both ADCs are now in slave mode.
2022-02-07 14:41:25 +02:00
alin724 b63ebca292 projects/cn0506_rmii/*: Add util_mii_to_rmii library to project 2022-02-03 10:23:12 +02:00
alin724 170ce42e3e util_mii_to_rmii: Initial commit 2022-02-03 10:23:12 +02:00
AndreiGrozav 3da9d9fcb4 pluto_ng: Initial commit 2022-02-03 09:56:13 +02:00
Iacob_Liviu 7dae0858b0 de10nano: changed quartus version to 20.1.1 2022-01-31 14:10:51 +02:00
AndreiGrozav 38f3627695 ad_dds: Fix DDS start samples
When using a CLK_RATIO > 1 the first n samples(n=CLK_RATIO) after sync, are
noisy. This is because the phase accumulator data is passed to the phase to
amplitude converter, during the phase synchronization step.
2022-01-31 14:07:11 +02:00
sergiu arpadi bc5974d789 ad77681evb: Fix irq overlap
spi engine irq signal was overwriting fmc iic irq
2022-01-31 12:32:31 +02:00
Dan Hotoleanu f34b561e19 daq3: Parameterize JESD204 configuration values
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:47:01 +02:00
Dan Hotoleanu e8ff32d6df ad6676evb: Parameterize JESD204 configuration values
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:36:31 +02:00
Dan Hotoleanu 318523579f ad6676evb: Update to JESD204 TPL instantiation
Updated the JESD204 TPL instantation of the design.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:36:31 +02:00
Iulia Moldovan b26b4c00f0 ad9783: Clean-up parameters and module instances 2022-01-25 18:24:43 +02:00
Iulia Moldovan 9ca5ae07b2 ad9783: Add Readme.md 2022-01-25 17:16:30 +02:00
Laszlo Nagy 889447e900 axi_ad9361: make IODELAYCTRL insertion optional 2022-01-25 09:50:31 +02:00
Laszlo Nagy bc8e7881f2 axi_dmac: Hook up ID
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2022-01-25 09:50:22 +02:00
Dan Hotoleanu 530aca9754 daq2: Parameterize JESD204 configuration values
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-20 12:54:03 +02:00
Iulia Moldovan f3cf7508c8 ad9783: Update Makefile 2022-01-20 12:31:57 +02:00
Filip Gherman 4ec8797c7c adrv9009: Parameterize JESD204 configuration values 2022-01-13 10:15:05 +02:00
LIacob106 9d94f21d89 scripts/adi_xilinx_device_info_enc.tcl: Change regex for vcu128
The regex does not match vcu128 as Ultrascale+. It matches for Ultrascale.
2022-01-12 17:32:47 +02:00
Filip Gherman 6a92bd5925 adrv9371x: Parameterize JESD204 configuration values 2022-01-12 16:05:48 +02:00
Filip Gherman d8a418d8d0 projects/scripts/adi_board/tcl: Updated ad_xcvrcon procedure for parametrized projects 2022-01-12 16:05:18 +02:00
Filip Gherman 9d8097389c library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register 2022-01-12 13:43:20 +02:00
sergiu arpadi fc04198b2b adrc9361_ccfmc: Fix SFP pin locations 2022-01-12 13:43:06 +02:00
Dan Hotoleanu 86d2467f57 fmcjesdadc1: Parameterize JESD204 configuration values
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-12 13:28:42 +02:00
Filip Gherman 080925e8fe library/jesd204: tpl timing bug fix 2022-01-12 10:14:55 +02:00
Iulia Moldovan 3d000ee6a8 ad9783_zcu102_dev: Initial commit 2022-01-07 14:04:08 +02:00