Commit Graph

13 Commits (5db7574dcebcca6ec54056d5801ac225262436e2)

Author SHA1 Message Date
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
aholtzma 2ff5420630 Update system_top.v
Add a comment that the spi CS decoding is tied to a setting in the device tree.
2020-11-02 16:59:08 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Adrian Costina bde2d1d66d fmcomms8: zcu102: Leave the SPI constraint at 25 MHz 2020-09-25 11:54:12 +03:00
Adrian Costina f8c2eb12d4 fmcomms8: zcu102: Remove the test pins, as they are not connected 2020-09-25 11:54:12 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Adrian Costina 19b7986486 fmcomms8: Fix SPI timing
The maximum SPI rate set to 10MHz
2020-03-16 13:26:20 +02:00
Adrian Costina fad52175d1 fmcomms8: Fix spi connection 2020-03-06 16:07:02 +02:00
Adrian Costina e51d9372cd fmcomms8: ZCU102: Added DAC FIFO 2020-02-10 11:23:52 +02:00
Adrian Costina 016a1d540d fmcomms8: ZCU102: Initial commit 2020-02-10 11:23:52 +02:00