Commit Graph

11 Commits (5db7574dcebcca6ec54056d5801ac225262436e2)

Author SHA1 Message Date
Laszlo Nagy 0261eade0c zynq:all: fix SPI clock constraint
According to data sheets the EMIO SPI controller maximum frequency is
just 25MHz. Constrain the SPI clock accordingly.
2019-08-09 16:39:56 +03:00
Laszlo Nagy 5986e87a1f zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS 2019-05-30 14:55:11 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Lars-Peter Clausen f232a36141 common: Place HDMI interface registers into the IOB
The paths from the HDMI interface registers to the IO pads are
unconstrained. This means the P&R can in theory put the register anywhere
which could lead to stability issues on the interface, depending on what
else is in the fabric. To get predictable delays for the register to IO pad
path place the register into the IOB section.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
Istvan Csomortani 59e610be09 zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc 2014-12-17 19:07:43 +02:00
Rejeesh Kutty ed7f8b4908 plddr3: sys-rst from board pushbutton 2014-12-15 12:58:44 -05:00
Rejeesh Kutty 6d76e0b768 zc706: remove top level constraints 2014-10-15 14:51:02 -04:00
Istvan Csomortani dd7bac41c1 daq1 : Update project to 2014.2
- Cores are upadted
  - Concat module does not swap output anymore
  - Clock signal name ps7_clk_* changed to clk_fpga_*
2014-09-22 17:33:50 +03:00
Adrian Costina a49eb5853b ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
Adrian Costina 6c6cab0e16 fmcomms2: ZC706 modified constraints for linux build machines
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
2014-08-01 17:34:36 +03:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00