4 Commits (5db7574dcebcca6ec54056d5801ac225262436e2)

Author	SHA1	Message	Date
Istvan Csomortani	3f7f2f9c9f	util_adcfifo: Fix the address generation and read logic	2019-05-28 08:48:16 +03:00
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Rejeesh Kutty	bb9cb86f34	adc/dac- fifo constraints	2016-08-11 10:00:41 -04:00
Rejeesh Kutty	86a70b3054	adcfifo: added	2015-04-07 15:43:02 -04:00