Laszlo Nagy
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d94ec80e08
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Update README.md
Correct the ZCU102 PL DDR memory controller interface width and speed based on available options of the MIG
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2021-10-05 11:59:51 +03:00 |
David Winter
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a89d0e6176
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data_offload: Fix AXI register map
Signed-off-by: David Winter <david.winter@analog.com>
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2021-08-06 11:55:24 +03:00 |
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David Winter
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537a284115
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data_offload: Fix readme images
Signed-off-by: David Winter <david.winter@analog.com>
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2021-08-06 11:55:24 +03:00 |
Istvan Csomortani
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6516b09a31
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data_offload: Update README and generic block design
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2021-08-06 11:55:24 +03:00 |
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Istvan Csomortani
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86b611c1f7
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data_offload: Initial commit
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2021-08-06 11:55:24 +03:00 |