In phase aligned mode the fPLL uses an external feedback path to better
align the phase of the PLL output to the phase of the external reference
clock.
This mode is required for deterministic latency to be able to sample SYSREF
which is source synchronous to the external reference clock signal.
So far phase aligned mode had been disabled since manual PLL calibration
would fail in this mode under certain (unknown) circumstances and dynamic
reconfiguration of the PLL would not work.
The latest Intel Arria 10 transceiver datasheet contains instructions for
the proper calibration sequence to make it work when the PLL is configured
for phase aligned mode. Software has been updated accordingly, so enable
phase aligned mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Refactor the AXI4 stream FIFO implementation.
- Define a single address generator which supports both single and double
clock mode. (synchronous and asynchronous)
- Fix FIFO status bits (empty/full). NOTE: In asynchronous mode the
flags can have a several clock cycle delay in function of the upstream/downstream
clock ratio.
- In synchronous none FIFO mode (ADDRESS_WIDTH==0), the module acts as
an AXI4 stream pipeline.
Allow channels received from dma to re-map to other channels, e.g. allowing
broadcasting the same channel to all channels.
The feature is selectable with synthesis parameter and disabled by default.
Build a large mux from smaller ones defined by the REQ_MUX_SZ parameter
Use EN_REG to add a register at the output of the small muxes to help
timing closure.
This commit adds two fields:
1. source channel selection - Sets the channel number the for the source data.
2. DMA enable mask - When this bit is set do not drive the enable line
towards the DMA interface.
This feature will allow the user to hold(indefinitely) the last sample, from an
ongoing DMA transfer, simple or cyclic(stooped by user or trigger).
This commit also adds as functionality option:
-synchronized stop between the two channels(DMAs)
-stop by trigger
This reverts commit 0402ce85e4
and reverts commit 164aa97ec3.
The trigger pulse generation must be handled outside of the
SPI Engine framework.
It is recommanded to be done in system level using a PWM
generator or an external signal.
fixed critical warnings generated when the NUM_OF_CLK_MONS parameter
is set to 0 and the constraints written in up_clock_mon_constr.xdc
cannot be applied; removed up_clock_mon_constr.xdc from ip core.
When the link is disabled the events can be ignored.
This is required by the free running event counter that can catch
invalid events during startup cased for example by an invalid link clock.
If the lane looses synchronization due invalid characters or disparity
error the lane alignment monitor checks random input which results in
irrelevant reporting of frame alignment error.
If all lanes are synchronized (CGS state machine is in DATA phase) for long
enough therefore the link is also synchronized/DATA phase reset the error
counter since the accumulated values during INIT/CHECK are irrelevant.
These errors are handled by the per-lane CGS state machine.
All errors accumulated during INIT/CHECK phase of CGS are relevant only
if the link is unable to reach the DATA phase.
The link stays in DATA phase unless software resets it,
so all errors accumulated during the DATA phase are relevant.
The previous implementation of the de-glitch only delayed the assertion
of the SYNC phase by 64 clock cycles with the DEGLITCH state but if meanwhile
one of the lanes got into a bad state cgs_ready de-asserted the state machine
continued to go SYNCHRONIZED (DATA) state.
This change extends the required number of consecutive cycles while all lanes
must stay in data phase before moving the link to SYNCHRONIZED state from 8 to 256;
This increases the reliability of link bring-up without needing extra
link restarts from software side.
Add statistics for :
- number of link enable events
- number of interrupt events (regardless of mask)
0x0B0 0x2C0 Stats Control Register
[0] - Write 1 to clear stat registers
0x0B1 0x2C4 Link Enable Stat Register
[15:0] Number of times the link was enabled from power-on or from last
stat clear
0x0B4 0x2D0 IRQ Stat Register 0
[31:16] IRQ 1 counter
[15:0] IRQ 0 counter
0x0B5 0x2D4 IRQ Stat Register 1
[31:16] IRQ 3 counter
[15:0] IRQ 2 counter
0x0B6 0x2D8 IRQ Stat Register 2
[31:16] IRQ 5 counter
[15:0] IRQ 4 counter
0x0B7 0x2DC IRQ Stat Register 3
[31:16] IRQ 7 counter
[15:0] IRQ 6 counter
Quartus Standard 19.1 throw a critical warning for registers that have
different reset and initial power-up level.
Do not initialize those registers so we can get rid of the warning.
Define both AXI4 Memory Mapped and microprocessor interface for the
reigster map, then activate/deactive one of it in fucntion of the memory
interface type parameter.
Define the missing status_sync interface, which should be connected to
the offload.
Context switching with a parameter is not a good idea. The simulator
may evaluate both branch of the IF statement, even though the inactive
branch may not be valid.
Use if..generate to make the code more robust for both synthesizers and
simulators.
Lars-Peter Clausen
AndreiGrozav
Istvan Csomortani
Laszlo Nagy
Adrian Costina
sergiu arpadi
Josh Blum
stefan.raus