482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
2b274f945f
ad9081_fmca_ebz: Reset cpack with Rx data offload
2022-08-01 12:47:26 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
20b89ddd99
ad9081_fmca_ebz/vcu128: Make second sync CMOS and GPIO controllable
2022-05-26 09:13:05 +03:00
97b92565b2
Makefile: Replace util_fifo2axi_bridge with util_hbm
2022-04-28 14:31:32 +03:00
fa168fafe0
ad9081_fmca_ebz:vcu128: Disable offload bypass
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The internal bypass FIFO has poor timing performance,
when using HBM data can be passed always through the external memory
without storage length constraints, so no need for the internal bypass FIFO.
2022-04-28 14:31:32 +03:00
c57015f80e
ad9081_fmca_ebz/vcu128: Use HBM for data offload cores
2022-04-28 14:31:32 +03:00
8df1d8eade
ad9081_fmca_ebz: Update parameter description
2022-03-11 13:16:22 +02:00
1ec0993d33
ad9081_fmca_ebz/vcu128: Remove ref clock replica
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Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-22 16:18:29 +02:00
e76f287e73
ad9081_fmca_ebz:vcu128: Initial version
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* 4Txs / 4Rxs per MxFE
* Tx I/Q Rate: 250 MSPS
* Rx I/Q Rate: 250 MSPS
* DAC JESD204B: Mode 9, L=4, M=8, N=N'=16
* ADC JESD204B: Mode 10, L=4, M=8, N=N'=16
* DAC-Side JESD204B Lane Rate: 10Gbps
* ADC-Side JESD204B Lane Rate: 10Gbps
2021-11-19 18:08:16 +02:00
Iacob_Liviu
Laszlo Nagy
Iulia Moldovan